Cypress Semiconductor FX2LP Technické informace stáhnout pdf (Strana 405)

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Chapter 15. Registers Page 15-85

The GPIF Control pins (CTL[5:0]) have several output modes:

• CTL[3:0] can act as CMOS outputs (optionally tristatable) or open-drain outputs.

• CTL[5:4] can act as CMOS outputs or open-drain outputs.

If CTL[3:0] are configured to be tristatable, CTL[5:4] are not available.

During the IDLE State, the state of CTL[5:0] depends on the following register bits:

• TRICTL (GPIFCTLCFG.7).

• GPIFCTLCFG[5:0]

• GPIFIDLECTL[5:0].

The combination of these bits defines CTL5:0 during IDLE as follows:

• If TRICTL is 0, GPIFIDLECTL[5:0] directly represent the output states of CTL5:0 during

the IDLE State. The GPIFCTLCFG[5:0] bits determine whether the CTL5:0 outputs are

CMOS or open-drain: If GPIFCTLCFG.x = 0, CTLx is CMOS; if GPIFCTLCFG.x = 1, CTLx

is open-drain.

• If TRICTL is 1, GPIFIDLECTL[7:4] are the output enables for the CTL[3:0] signals, and

GPIFIDLECTL[3:0] are the output values for CTL[3:0]. CTL4 and CTL5 are unavailable in

this mode.

Table 15-16. CTL[5:0] Output Modes

TRICTL

(GPIFCTLCFG.7)

GPIFCTLCFG[6:0] CTL[3:0] CTL[5:4]

0 0 CMOS, Not Tristatable CMOS, Not Tristatable

0 1 Open-Drain Open-Drain

1 X CMOS, Tristatable Not Available

1 2 ... 400 401 402 403 404 405 406 407 408 409 410 ... 459 460

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