Cypress Semiconductor FX2LP Technické informace stáhnout pdf (Strana 271)

Chapter 12. Instruction Set Page 12-5

12.1.1 Instruction Timing

Instruction cycles in the FX2 are 4 clock cycles in length, as opposed to the 12 clock cycles per

instruction cycle in the standard 8051. For full details of the instruction-cycle timing differences

between the FX2 and the standard 8051, see

Section 11.3, "Performance Overview"

In the standard 8051, all instructions except for MUL and DIV take one or two instruction cycles to

complete. In the FX2, instructions can take between one and five instruction cycles to complete.

For calculating the timing of software loops, etc., use the “Cycles” column from Table 12-2. The

“Bytes” column indicates the number of bytes occupied by each instruction.

By default, the FX2’s timer/counters run at 12 clock cycles per increment so that timer-based

events have the same timing as with the standard 8051. The timers can also be configured to run

at 4 clock cycles per increment to take advantage of the higher speed of the FX2’s CPU.

12.1.2 Stretch Memory Cycles (Wait States)

The FX2 can execute a MOVX instruction in as few as 2 instruction cycles. However, it is some-

times desirable to stretch this value (for example to access slow memory or slow memory-mapped

peripherals such as USARTs or LCDs). The FX2’s “stretch memory cycle” feature enables FX2

firmware to adjust the speed of data memory accesses (program-memory code fetches are not

affected).

JZ rel Jump if accumulator = 0 2 3 60

JNZ rel Jump if accumulator is non-zero 2 3 70

CJNE A, direct, rel Compare A to direct byte; jump if not equal 3 4 CY B5

CJNE A, #d, rel Compare A to immediate; jump if not equal 3 4 CY B4

CJNE Rn, #d, rel Compare register to immediate;

jump if not equal

34CY B8-BF

CJNE @ Ri, #d, rel Compare data memory to immediate;

jump if not equal

34CY B6-B7

DJNZ Rn, rel Decrement register; jump if not zero 2 3 D8-DF

DJNZ direct, rel Decrement direct byte; jump if not zero 3 4 D5

Miscellaneous

NOP No operation 1 1 00

There is an additional reserved opcode (A5) that performs the same function as NOP.

Table 12-2. FX2 Instruction Set (Continued)

Mnemonic Description Bytes Cycles

PSW

Flags

Affected

Opcode

(Hex)

1 2 ... 266 267 268 269 270 271 272 273 274 275 276 ... 459 460

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Cypress Semiconductor FX2LP Technické informace Strana 271