Cypress Semiconductor FX2LP Technické informace stáhnout pdf (Strana 17)

List of Figures xvii

(List of Figures)

Figure 14-2. Timer 0/1 - Mode 2 .........................................................................................................14-6

Figure 14-3. Timer 0 - Mode 3 ............................................................................................................14-7

Figure 14-4. Timer 2 - Timer/Counter with Capture ..........................................................................14-10

Figure 14-5. Timer 2 - Timer/Counter with Auto Reload ...................................................................14-11

Figure 14-6. Timer 2 - Baud Rate Generator Mode ..........................................................................14-12

Figure 14-7. Serial Port Mode 0 Receive Timing - Low Speed Operation ........................................14-18

Figure 14-8. Serial Port Mode 0 Receive Timing - High Speed Operation .......................................14-18

Figure 14-9. Serial Port Mode 0 Transmit Timing - Low Speed Operation .......................................14-19

Figure 14-10. Serial Port Mode 0 Transmit Timing - High Speed Operation ......................................14-19

Figure 14-11. Serial Port 0 Mode 1 Transmit Timing ..........................................................................14-23

Figure 14-12. Serial Port 0 Mode 1 Receive Timing ...........................................................................14-24

Figure 14-13. Serial Port 0 Mode 2 Transmit Timing ..........................................................................14-25

Figure 14-14. Serial Port 0 Mode 2 Receive Timing ...........................................................................14-26

Figure 14-15. Serial Port 0 Mode 3 Transmit Timing ..........................................................................14-27

Figure 14-16. Serial Port 0 Mode 3 Receive Timing ...........................................................................14-27

Figure 15-1. Register Description Format ..........................................................................................15-2

Figure 15-2. Single Instruction to Read Port B ...................................................................................15-4

Figure 15-3. Single Instruction to Write to Port C ...............................................................................15-4

Figure 15-4. Use Bit 2 to set PORTD - Single Instruction ..................................................................15-9

Figure 15-5. Use OR to Set Bit 3 ........................................................................................................15-9

Figure 15-6. GPIF Waveform Descriptor Data .................................................................................15-13

Figure 15-7. CPU Control and Status ...............................................................................................15-13

Figure 15-8. Interface Configuration (Ports, GPIF, slave FIFOs) .....................................................15-14

Figure 15-9. IFCLK Configuration .....................................................................................................15-15

Figure 15-10. Slave FIFO FLAGA-FLAGD Pin Configuration ............................................................15-18

Figure 15-11. Restore FIFOs to Reset State ......................................................................................15-20

Figure 15-12. Breakpoint Control .......................................................................................................15-20

Figure 15-13. Breakpoint Address High .............................................................................................15-21

Figure 15-14. Breakpoint Address Low ..............................................................................................15-21

Figure 15-15. 230 Kbaud Internally Generated Reference Clock .......................................................15-22

Figure 15-16. Slave FIFO Interface Pins Polarity ...............................................................................15-22

Figure 15-17. Chip Revision ID ..........................................................................................................15-23

Figure 15-18. Chip Revision Control ..................................................................................................15-24

Figure 15-19. Endpoint 1-OUT/Endpoint 1-IN Configurations ............................................................15-26

Figure 15-20. Endpoint 2 Configuration ..............................................................................................15-27

Figure 15-21. Endpoint 4 Configuration ..............................................................................................15-27

Figure 15-22. Endpoint 6 Configuration ..............................................................................................15-27

Figure 15-23. Endpoint 8 Configuration ..............................................................................................15-27

Figure 15-24. Endpoint 2, 4, 6 and 8 /Slave FIFO Configuration .......................................................15-29

Figure 15-25. Endpoint 2 and 6 AUTOIN Packet Length High ...........................................................15-31

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Cypress Semiconductor FX2LP Technické informace Strana 17