Cypress Semiconductor FX2LP Technické informace stáhnout pdf (Strana 198)

EZ-USB FX2 Technical Reference Manual

Page 10-8 EZ-USB FX2 Technical Reference Manual v2.1

10.2.6 Three GSTATE OUT signals

Three GPIF State lines, GSTATE[2:0], are available as an alternate configuration of PORTE[2:0].

These default to general-purpose inputs; setting GSTATE (IFCONFIG.2) to 1 selects the alternate

configuration and overrides PORTECFG[2:0] bit settings.

The GSTATE[2:0] pins output the current GPIF State number; this feature is typically used only

while debugging GPIF waveforms.

10.2.7 8/16-Bit Data Path, WORDWIDE = 1 (default) and WORDWIDE = 0

When the FX2 is configured for GPIF Master mode, PORTB is always configured as FD[7:0].

If any of the WORDWIDE bits (EPxFIFOCFG.0) are set to 1, PORTD is automatically configured

as FD[15:8]. If all the WORDWIDE bits are cleared to 0, PORTD is available for general-purpose

I/O.

10.2.8 Byte Order for 16-bit GPIF Transactions

Data is sent over USB in packets of 8-bit bytes, not 16-bit words. When the FIFO Data bus is 16

bits wide, the first byte in every pair sent over USB is transferred over FD[7:0] and the second byte

is transferred over FD[15:8].

10.2.9 Interface Clock (IFCLK)

The GPIF interface can be clocked from either an internal or an external source. The FX2’s inter-

nal clock source can be configured to run at either 30 or 48 MHz, and it can optionally be output on

the IFCLK pin. If the FX2 is configured to use an external clock source, the IFCLK pin can be

driven at any frequency between 5 MHz and 48 MHz. On power-on reset, the FX2 defaults to the

internal source at 48 MHz, normal polarity, with the IFCLK output disabled. See Figur e10-4.

IFCONFIG.7 selects between internal and external sources: 0 = external, 1 = internal.

IFCONFIG.6 selects between the 30- and 48-MHz internal clock: 0 = 30 MHz, 1 = 48 MHz. This bit

has no effect when IFCONFIG.7 = 0.

IFCONFIG.5 is the output enable for the internal clock source: 0 = disable, 1 = enable. This bit has

no effect when IFCONFIG.7 = 0.

IFCONFIG.4 inverts the polarity of the interface clock (whether it’s internally or externally

sourced): 0 = normal, 1 = inverted. IFCLK inversion can make it easier to interface the FX2 with

certain external circuitry; Figure 10-5, for example, demonstrates the use of IFCLK inversion in

order to ensure a long-enough setup time for reading peripheral signals.

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Cypress Semiconductor FX2LP Technické informace Strana 198