Cypress Semiconductor FX2LP Technické informace stáhnout pdf (Strana 148)

EZ-USB FX2 Technical Reference Manual

Page 8-12 EZ-USB FX2 Technical Reference Manual v2.1

transfer logic. As soon as one buffer becomes available, FULL will be cleared to 0 and NPAK will

decrement by one, indicating that all but one of the buffers are committed to USB (i.e., one is avail-

able for firmware access). As IN buffers are transferred over USB, NPAK decrements to indicate

the number still pending, until all are sent and NPAK=0.

EMPTY

While FULL and EMPTY apply to transfers in both directions, EMPTY is more useful for OUT

transfers. EMPTY=1 means that the buffers are empty; all received packets (2, 3, or 4, depending

on the buffering depth) have been serviced.

STALL

Firmware sets STALL=1 to instruct the FX2 to return the STALL PID (instead of ACK or NAK) in

response to an IN or OUT transfer. The FX2 will continue to respond to IN or OUT transfers with

the STALL PID until the firmware clears this bit.

8.6.2.4 EP2BCH:L, EP4BCH:L, EP6BCH:L, EP8BCH:L

Endpoints EP2 and EP6 have 11-bit byte count registers to account for their maximum buffer sizes

of 1024 bytes. Endpoints EP4 and EP8 have 10-bit byte count registers to account for their maxi-

mum buffer sizes of 512 bytes.

The byte count registers function similarly to the EP0 and EP1 byte count registers:

• For an IN transfer, the firmware loads the byte count registers to arm the endpoint (if

EPxBCH must be loaded, it should be loaded first, since the endpoint is armed when

EPxBCL is loaded).

• For an OUT transfer, the firmware reads the byte count registers to determine the number

of bytes in the buffer, then writes any value to the low byte count register to re-arm the

endpoint. See the “Skip” section, below, for further details.

SKIP

Normally, the CPU interface and outside-logic interface to the endpoint FIFOs are independent,

with separate sets of control bits for each interface. The AUTOOUT mode and the SKIP bit imple-

ment an “overlap” between these two domains. A brief introduction to the AUTOOUT mode is

given below; full details appear in Chapter 9, "Slave FIFOs."

When outside logic is connected to the interface FIFOs, the normal data flow is for the FX2 auto-

matically to commit OUT data packets to the outside interface FIFO as they become available.

This ensures an uninterrupted flow of OUT data from the host to the outside world, and preserves

the high bandwidth required by high speed mode.

In some cases, it may be desirable to insert a “hook” into this data flow, so that -- rather than the

FX2 automatically committing the packets to the outside interface as they are received over USB,

firmware receives an interrupt for every received OUT packet, then has the option to either commit

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Cypress Semiconductor FX2LP Technické informace Strana 148