Cypress Semiconductor FX2LP Technické informace stáhnout pdf (Strana 110)

EZ-USB FX2 Technical Reference Manual

Page 4-20 EZ-USB FX2 Technical Reference Manual v2.1

The registers associated with the individual FIFO/GPIF interrupt sources are described in

Chapter

15, "Registers"

and Section 8.6, "CPU Control of FX2 Endpoints". Each interrupt source has an

enable (IE) and a request (IRQ) bit. Firmware sets the IE bit to 1 to enable the interrupt. The FX2

sets an IRQ bit to 1 to request an interrupt, and the firmware clears an IRQ bit by setting it to 1.

The main FIFO/GPIF interrupt request is cleared by

clearing

the EXIF.6 bit

to 0

; each individual

FIFO/GPIF interrupt is cleared by

setting

its IRQ bit

to 1

4.8 FIFO/GPIF-Interrupt Autovectors

The main FIFO/GPIF interrupt is shared by 14 interrupt sources. To save the code and processing

time which normally would be required to sort out the individual FIFO/GPIF interrupt source, the

FX2 provides a second level of interrupt vectoring, called Autovectoring. When a FIFO/GPIF inter-

rupt is asserted, the FX2 pushes the program counter onto its stack then jumps to address

0x0053, where it expects to find a “jump” instruction to the FIFO/GPIF Interrupt service routine.

The FX2 jump instruction is encoded as follows:

If Autovectoring is enabled (AV4EN=1 in the INTSETUP register), the FX2 substitutes its

INT4VEC byte (see Table 4-14) for the byte at address 0x0055. Therefore, if the high byte (“page”)

of a jump-table address is preloaded at location 0x0054, the automatically-inserted INT4VEC byte

at 0x0055 will direct the jump to the correct address out of the 14 addresses within the page.

Important

It is important in any FIFO/GPIF Interrupt Service Routine (ISR) to clear the main INT4 Inter-

rupt before clearing the individual FIFO/GPIF interrupt request latch. This is because as

soon as the individual FIFO/GPIF interrupt is cleared, any pending FIFO/GPIF interrupt will

immediately try to generate another main FIFO/GPIF Interrupt. If the main INT4 IRQ bit has

not been previously cleared, the pending interrupt will be lost.

Table 4-15. FX2 JUMP Instruction

Address Op-Code Hex Value

0x0053 LJMP 0x02

0x0054 AddrH 0xHH

0x0055 AddrL 0xLL

1 2 ... 105 106 107 108 109 110 111 112 113 114 115 ... 459 460

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