Cypress Semiconductor FX2LP Technické informace stáhnout pdf (Strana 315)

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Chapter 14. Timers/Counters and Serial Interface Page 14-23

of a start bit is detected, the divide-by-16 counter used to generate the receive clock is reset to

align the counter rollover to the bit boundaries.

For noise rejection, the serial port establishes the content of each received bit by a majority deci-

sion of 3 consecutive samples in the middle of each bit time. For the start bit, if the falling edge on

the RXD0 (or RXD1) pin is not verified by a majority decision of 3 consecutive samples (low), then

the serial port stops reception and waits for another falling edge on the RXD0 (or RXD1) pin.

At the middle of the stop bit time, the serial port checks for the following conditions:

• RI_0 (or RI_1) = 0

• If SM2_0 (or SM2_1) = 1, the state of the stop bit is 1

(If SM2_0 (or SM2_1) = 0, the state of the stop bit doesn’t matter.

If the above conditions are met, the serial port then writes the received byte to the SBUF0 (or

SBUF1) Register, loads the stop bit into RB8_0 (or RB8_1), and sets the RI_0 (or RI_1) Bit. If the

above conditions are not met, the received data is lost, the SBUF Register and RB8 Bit are not

loaded, and the RI Bit is not set.

After the middle of the stop bit time, the serial port waits for another high-to-low transition on the

(RXD0 or RXD1) pin.

Figure 14-11. Serial Port 0 Mode 1 Transmit Timing

Write to

SBUF0

RI_0

TXD0

RXD0

RXD0OUT

SHIFT

TX CLK

TI_0

D0 D1 D2 D3 D4 D5 D6 D7

STOP

START

1 2 ... 310 311 312 313 314 315 316 317 318 319 320 ... 459 460

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