Cypress Semiconductor Quad HOTLink II CYV15G0404RB Uživatelská příručka stáhnout pdf (Strana 14)

Quad Independent Channel

HOTLink II™ CYV15G0404DXB

Video PHY Demonstration Board

Page 14 of 92

5.1 Setting the SDI Data Rate

The appropriate data rate is set by selecting the appropriate button in the Tx/Rx Rate Box of the GUI. The various data rate

options are 270 Mb/s (SD-SDI/SMPTE 259M-C), 360 Mb/s (SMPTE 259M-D), 540 Mb/s (SMPTE 344M) or 1485 Mb/s (HD-SDI).

See Figure 5-2 for a picture of this GUI panel. The FR (Full Rate) check box adjacent to the 1485-Mb/s option is for setting the

source clock frequency for HD-SDI as either full-rate (148.5 MHz) or half-rate (74.25 MHz), via the programmable clock. When

the check-box is checked, a full-rate 148.5-MHz clock is used, and when unchecked, a 74.25-MHz clock is used. This button is

active only when the 1485-Mb/s button is selected.

If the programmable clock option is selected, the data rate setting in the GUI controls the output frequency of the programmable

clock. If the external clock option is selected, the user must ensure that the external clock frequency matches the data rate setting

in the GUI. If the on-board 74.25-MHz crystal oscillator is used, the 1485 Mb/s option must be selected with the FR box left

unchecked. See Section 4.2 for information on selecting clock options.

RxSec Receive data via INA2 (supports SD only)

Tx/Rx

Rate

270 Mb/s SD-SDI: SMPTE 259M-C

360 Mb/s SD-SDI: SMPTE 259M-D

540 Mb/s SD-SDI: SMPTE 344M

1485 Mb/s HD-SDI: SMPTE 292M

Auto Rate Detect Programmable clock is reconfigured to the incoming video data rate and all other Tx/Rx Rate

buttons will display which frequency the programmable clock is set to.

FR Setting the source clock frequency for HD-SDI as either full-rate (148.5 MHz) or half rate

(74.25 MHz). When the check-box is checked, a full-rate 148.5 MHz clock is used; when

unchecked, a 74.25 MHz clock is used.

Source

EG1 Color Bars The FPGA generates EG1 color bars, which will be transmitted out on OUTA1 or OUTA2 or

both.

Grey The FPGA generates a uniform grey pattern, which will be transmitted out on OUTA1 or

OUTA2 or both.

RP178/198 The FPGA generates RP178/198 pattern (a pink half-frame on top of a grey half-frame, which

will be transmitted out on OUTA1 or OUTA2 or both.

RP 178/198 Alt. The FPGA generates an alternative set of the RP178/198 pattern which will be transmitted

out on OUTA1 or OUTA2 or both.

Reclocker Reclock the recovered data from the clock and data recovery unit and retransmit it through

the serial outputs of the same channel.

Up Convert Ch B Functionality not yet implemented.

MCL Maximum Cable Length: for normal operation there is no need for the user to touch this (i.e.

leave at 300m). If user would like to test at specific cable lengths then the bar can be set to

the desired setting.

Status Auto Rate Locked Button selected when the correct data rate is detected.

CD Carrier Detect: Button selected when the amplitude of the signal on equalizer is above the

MCL threshold.

LFI Link Fault Indicator: Button automatically selected when HOTLink II CYV15G0404DXB does

NOT receive a valid serial signal on the relevant channel.

CRC Errors Cyclic Redundancy Check Errors Indicator Bar: indicator bar indicates data reception errors.

CLI Cable Length Indicator: estimates length of the cable being used for transmitting/receiving

data. Output from cable equalizer.

Channel

Run/Stop Hitting run configures the channel with the applied settings; hitting stop ends operation and

powers down channel A.

Table 5-1. Summary of GUI Button Functionality (Shown Here for Channel A) (continued)

Group Button Name Functionality (On Click)

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1 2 ... 9 10 11 12 13 14 15 16 17 18 19 ... 91 92

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