Cypress Semiconductor Quad HOTLink II CYV15G0404RB Uživatelská příručka Strana 31
- Strana / 92
- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
Quad Independent Channel
HOTLink II™ CYV15G0404DXB
Video PHY Demonstration Board
Page 31 of 92
Figure A-1. Top Level Schematic
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
LS7652
CypressMolson-TopLevel
2
01 12
G. Cosens
Size Drawin g Nu mbe r Revisio n
Date:
Fil e:
Sheet of
Drawn By:Top Level.SchDoc
7/ 6/ 2004
C
Linear Systems Ltd.
OUTA1+
OUTA1-
OUTA2+
OUTA2-
INA1 +
INA1 -
INA2 +
INA2 -
OUTB1+
OUTB1-
OUTB2-
OUTB2+
INB1+
INB1-
INB2+
INB2-
OUTC1+
OUTC1-
OUTC2+
OUTC2-
INC1+
INC1-
INC2+
INC2-
OUTD1+
OUTD1-
OUTD2+
OUTD2-
IND1 +
IND1 -
IND2 +
IND2 -
TXDA [7 . .0]
TXDB[7.. 0]
TXDC[7.. 0]
TXDD [7 . .0]
TXCTA[1..0 ]
TXCTB[1..0]
TXCTC[1..0]
TXCTD[1..0 ]
RXDA[7..0]
RXDB[7 .. 0]
RXDC[7 .. 0]
RXDD[7..0]
RXSTA [2..0]
RXSTB[2 ..0]
RXSTC[2 ..0]
RXSTD [2..0]
TXCLKOA
TXCLKOB
TXCLKOC
TXCLKOD
RXCLKA+
RXCLKA-
RXCLKB+
RXCLKB-
RXCLKC+
RXCLKC-
RXCLKD+
RXCLKD-
TXCLKA
TXCLKB
TXCLKC
TXCLKD
REFCLKA+
REFCLKB+
REFCLKC+
REFCLKD+
HR ESE T#
SPDSELA
SPDSELB
SPDSELC
SPDSELD
LPENA
LPENC
LPENB
LPEND
INSELA
INSELB
INSELC
INSELD
ULC A
ULC B
ULC C
ULC D
LDTDEN
DATA [7 ..0 ]
ADDR [3..0]
WREN
LFIA
LFIB
LFIC
LFID
REFCLKB-
REFCLKC-
REFCLKD-
RCLKENA
RC L KENB
RC L KENC
RCLKEND
REFCLKA-
TMRESET#
TMS
TCLK
TDI
TDO
TXERRA
TXERRB
TXERRC
TXERRD
CYV15G040 3
CYV15G040 3.Sch Doc
TXDA [7 . .0]
TXDB[7.. 0]
TXDC[7.. 0]
TXDD [7 . .0]
TXCTA[1..0 ]
TXCTB[1..0]
TXCTC[1..0]
TXCTD[1..0 ]
TXCLKOA
TXCLKOB
TXCLKOC
TXCLKOD
TXCLKA
TXCLKB
TXCLKC
TXCLKD
RXDA[7..0]
RXDB[7 .. 0]
RXDC[7 .. 0]
RXDD[7..0]
RXSTA [2..0]
RXSTB[2 ..0]
RXSTC[2 ..0]
RXSTD [2..0]
RXCLK A+
RXCLK B+
RXCLK C+
RXCLK D+
RXCLK A-
RXCLK B-
RXCLK C-
RXCLK D-
SD/ HDA
SD/ HDB
SD/ HDC
SD/ HDD
CD/MUTEA
CD/MUTEB
CD/MUTEC
CD/MUTED
PTXDA[9..0]
PTXDB[9..0]
PTXDC[9..0]
PTXDD[9..0]
PRXDA[9 ..0]
PRXDB [9..0]
PRXDC [9..0]
PRXDD[9 ..0]
FD[15..0 ]
CTL[2. .0]
RDY[1.. 0]
CL KOUT
IF C L K
LFIA
LFIB
LFIC
LFID
CD/MUTEB 2
CD/MUTED2
SSI/CD C2
SDI
SDO
SCL
SCSE
F1ASDI
F1nC S
F1DC LK
F1nCE
F1n C ONFIG
F1CONFIG_DON E
F1DATA0
PA7/*FLAGD/SLCS#
RES ET#
RCLKE ND
RCLKE NC
RCLKE NB
RCLKE NA
SPDSELA
SPDSELB
SPDSELC
SPDSELD
LPENA
LPENB
LPENC
LPEND
INS ELA
INS ELB
INS ELC
INS ELD
ULCA
ULCB
ULCC
ULCD
LDTDEN
PRXCLKA
PRXCLKB
PRXCLKC
PRXCLKD
PTXCLKA
PTXCLKB
PTXCLKC
PTXCLKD
F2CONFIG_DON E
F2n C ONFIG
F2nCE
F2DATA0
F2DC LK
F2nC S
F2ASDI
SCSE1
TMS
TCLK
TMRESET#
TDO
TDI
TXERRA
TXERRB
TXERRC
TXERRD
FCLKA+
FCLKA-
FCLKB+
FCLKB -
FCLKC+
FCLKC -
FCLKD+
FCLKD-
FPGA
FPGA.SchDoc
CLI A
CLI B
CLI C
CLI D
MCLADJA
MCLADJB
MCLADJC
MCLADJD
REFCLK A+
REFCLK B+
REFCLK C+
REFCLK D+
HR ES E T#
I2 SC L
I2 SDA
SCSE
SCL
SDO
SDI
DATA [7 ..0 ]
ADDR [ 3.. 0]
WREN
REFCLKA-
REFCLKB-
REFCLKC-
REFCLKD-
SCSE1
XR ES
XSC LK
XDAT A
FCLKD -
FCLKD +
FCLKC-
FCLKC+
FCLKB-
FCLKB+
FCLKA -
FCLKA +
Fle xibl e Clock & Configuration
Fle xibl e Clock & Configuration . SchDo c
I2 SDA
I2 SC L
CTL[2. .0]
RDY[1.. 0]
FD[1 5..0 ]
IF C L K
CL KO UT
DMINUS
DPL US
PA7/*FLAGD/SLCS#
F1CONFIG_DONE
F1n C ONFIG
F1n C E
F1DATA0
F1DC LK
F1n C S
F1ASDI
RESE T#
F2CONFIG_DONE
F2n C ONFIG
F2n C E
F2DATA0
F2DC LK
F2n C S
F2ASDI
XR ES
XSC LK
XD AT A
FX2 USB Microc on tr ol ler
FX2 USB Microc on tr ol ler. SchDoc
Power Sup ply
Power Sup ply. SchDoc
PTX DA[9..0]
PTXDB[9..0]
PTXDC[9..0]
PTX DD[9..0]
PRXDA[9 ..0]
PRXDB [9..0]
PRXDC [9..0]
PRXDD[9 ..0]
PTXCLKA
PTXCLKB
PTXCLKC
PTXCLKD
PRXCLKA
PRXCLKB
PRXCLKC
PRXCLKD
Parall el Inter faces
Parall el Inter faces.SchDoc
I2 C BUS
GPI F Int e rf ace
P ro gr a mmmin g In t e rf ac e
VBU S
1
D-
2
D+
3
GND
4
FRM1
5
FRM2
6
J20
USB-B
R167
1M
USB Connector
OUTA1 +
OUTA1-
OUTA2 +
OUTA2-
OUTB 1+
OUTB1-
OUTB 2+
OUTB2-
OUTC 1+
OUTC1-
OUTC 2+
OUTC2-
OUTD1 +
OUTD1-
OUTD2 +
OUTD2-
INA1+
INA1 -
INA2+
INA2 -
INB 1+
INB1-
INB 2+
INB2-
INC 1+
INC1-
INC 2+
INC2-
IND1+
IND1 -
IND2+
IND2 -
SD/ HDA
SD/ HDB
SD/ HDC
SD/ HDD
CD/MUTEB
CD/MUTEC
CD/MUTEA
CD/MUTED
MCLADJA
MCLADJB
MCLADJC
MCLADJD
CLI A
CLI B
CLI C
CLI D
CD/MUTEB2
CD/MUTED2
SSI/CDC2
Serial IO Interface
Serial IO Interface.SchDoc
RESET#
C158
4.7 n
S
TD3
TD4
TP1
1PIN
TP2
1PIN
TP3
1PIN
TP4
1PIN
Fiducial
FID1
Fiducial
FID2
Fiducial
FID3
Fiducial
FID4
Fiducial
FID5
Fiducial
FID6
TP5
1PIN
TP6
1PIN
TP7
1PIN
[+] Feedback
- Quad Independent Channel 1
- HOTLink II™ CYV15G0404DXB 1
- Video PHY Demonstration Board 1
- Users Guide 1
- Page 2 of 92 2
- Page 3 of 92 3
- LIST OF TABLES 4
- 1.0 Introduction 5
- 2.0 Kit Contents 5
- 3.0 Demo Board Features 6
- 4.0 Board Architecture 7
- 4.2 Clocking Architecture 8
- Programmable 10
- 4.4 Power Supply 11
- 5.0 GUI and Operating Modes 12
- [+] Feedback 13
- 5.1 Setting the SDI Data Rate 14
- 5.3 Standard 15
- 5.4 Transmit Test Pattern 16
- 5.5 Status 16
- 6.0 Sample Test Procedures 17
- 6.3 Tests 19
- Page 23 of 92 23
- Page 24 of 92 24
- Page 27 of 92 27
- Page 28 of 92 28
- 7.0 Summary 29
- 8.0 References 29
- Linear Syst ems Ltd 33
- Page 36 of 92 36
- Page 38 of 92 38
- (GERBER Files) 43
- Page 45 of 92 45
- Figure B-2. Top Overlay 45
- Page 64 of 92 64
- (Drill and Assembly) 65
- Page 66 of 92 66
- Figure C-1. Drill Placement 66
- Page 67 of 92 67
- Figure C-2. Assembly–Top View 67
- Page 68 of 92 68
- Video Demo Board 69
- Setting Configurations 85
- SD-SDI to HD-SDI Upconversion 86
- Channel B 87
- Channel A 87
- FPGA (U2) 87
- Board Modification 88
- FPGA(U2) 89
- PLL 1 PLL 2 JP11 89
- Page 91 of 92 91
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