
Document Number: 001-06422 Rev. *I Page 14 of 19
Hardware STORE Cycle
Parameter Alt Description
CY14B256L
Unit
Min Max
t
PHSB
t
HLHX
Hardware STORE Pulse Width 15 ns
t
DELAY
[17]
t
HLQZ ,
t
BLQZ
Time Allowed to Complete SRAM Cycle 1 70
μ
s
t
ss
[18, 19]
Soft Sequence Processing Time 70 us
Switching Waveforms
Figure 12. Hardware STORE Cycle
Figure 13. Soft Sequence Processing
[18, 19]
$GGUHVV $GGUHVV $GGUHVV $GGUHVV
6RIW6HTXHQFH
&RPPDQG
W
66
W
66
&(
$GGUHVV
9
&&
W
6$
W
&:
6RIW6HTXHQFH
&RPPDQG
W
&:
Notes
17.Read and Write cycles in progress before HSB
are given this amount of time to complete.
18.This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
19.Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See specific command.
Not Recommended for New Designs
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