Cypress Semiconductor FLEx36 CY7C0850AV Uživatelský manuál stáhnout pdf (Strana 17)

CY7C0850AV,CY7C0851V/CY7C0851AV

CY7C0852V/CY7C0852AV

CY7C0853V/CY7C0853AV

Document #: 38-06070 Rev. *K Page 17 of 36

JTAG Timing

Parameter Description

167/133/100

Unit

Min Max

JTAG

Maximum JTAG TAP controller frequency – 10 MHz

TCYC

TCK clock cycle time 100 – ns

TCK clock HIGH time 40 – ns

TCK clock LOW Time 40 – ns

TMSS

TMS setup to TCK clock rise 10 – ns

TMSH

TMS hold after TCK clock rise 10 – ns

TDIS

TDI setup to TCK clock rise 10 – ns

TDIH

TDI hold after TCK clock rise 10 – ns

TDOV

TCK clock LOW to TDO valid – 30 ns

TDOX

TCK clock LOW to TDO invalid 0 – ns

Figure 7. JTAG Switching Waveform

Test Clock

Test Mode Select

TCK

TMS

Test Data-In

TDI

Test Data-Out

TDO

TCYC

TMSH

TMSS

TDIS

TDIH

TDOX

TDOV

1 2 ... 12 13 14 15 16 17 18 19 20 21 22 ... 35 36

Synchronous Dual-Port RAM 1
Counter Readback Operation 9
Counter Increment Operation 9
Counter Hold Operation 9
Counter Reset Operation 9
Counter Load Operation 9
CY7C0852V/CY7C0852AV 10
CY7C0853V/CY7C0853AV 10
Performing a TAP Reset 13
Units of Measure 33
Products 36
PSoC Solutions 36

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