Cypress Semiconductor FLEx36 CY7C0850AV Uživatelský manuál stáhnout pdf (Strana 16)

CY7C0850AV,CY7C0851V/CY7C0851AV

CY7C0852V/CY7C0852AV

CY7C0853V/CY7C0853AV

Document #: 38-06070 Rev. *K Page 16 of 36

Output enable to data valid – 4.0 – 4.4 – 4.7 – 5.0 ns

OLZ

[24, 25]

OE to Low Z 0–0–0–0–ns

OHZ

[24, 25]

OE to High Z 0 4.0 0 4.4 0 4.7 0 5.0 ns

CD2

Clock to data valid – 4.0 – 4.4 – 4.7 – 5.0 ns

CA2

Clock to counter address valid – 4.0 – 4.4 – NA – NA ns

CM2

Clock to mask register readback valid – 4.0 – 4.4 – NA – NA ns

Data output hold after clock HIGH 1.0 – 1.0 – 1.0 – 1.0 – ns

CKHZ

[24, 25]

Clock HIGH to output High Z 0 4.0 0 4.4 0 4.7 0 5.0 ns

CKLZ

[24, 25]

Clock HIGH to output Low Z 1.0 4.0 1.0 4.4 1.0 4.7 1.0 5.0 ns

SINT

Clock to INT set time 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10 ns

RINT

Clock to INT reset time 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10 ns

SCINT

Clock to CNTINT set time 0.5 5.0 0.5 5.7 NA NA NA NA ns

RCINT

Clock to CNTINT reset time 0.5 5.0 0.5 5.7 NA NA NA NA ns

Port to Port Delays

CCS

Clock to clock skew 5.2 – 6.0 – 6.0 – 8.0 – ns

Master Reset Timing

Master reset pulse width 7.0 – 7.5 – 7.5 – 10.0 – ns

RSS

Master reset setup time 6.0 – 6.0 – 6.0 – 8.5 – ns

RSR

Master reset recovery time 6.0 – 7.5 – 7.5 – 10.0 – ns

RSF

Master reset to outputs inactive – 10.0 – 10.0 – 10.0 – 10.0 ns

RSCNTINT

Master reset to counter interrupt flag

reset time

– 10.0 – 10.0 – NA – NA ns

Switching Characteristics

Over the Operating Range (continued)

Parameter Description

-167 -133 -100

Unit

CY7C0850AV

CY7C0851V/AV

CY7C0852V/AV

CY7C0850AV

CY7C0851V/AV

CY7C0852V/AV

CY7C0853V

CY7C0853AV

CY7C0853V

CY7C0853AV

Min Max Min Max Min Max Min Max

Notes

24. This parameter is guaranteed by design, but it is not production tested.

25. Test conditions used are Load 2.

1 2 ... 11 12 13 14 15 16 17 18 19 20 21 ... 35 36

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Cypress Semiconductor FLEx36 CY7C0850AV Uživatelský manuál Strana 16

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