Cypress Semiconductor CY7C1364C Uživatelský manuál stáhnout pdf (Strana 22)

CY7C1364C

Document Number: 001-74592 Rev. *B Page 22 of 29

Figure 4. Write Cycle Timing

[22, 23]

Switching Waveforms (continued)

t

CYC

t

CL

CLK

ADSP

t

ADH

t

ADS

ADDRESS

t

CH

OE

ADSC

CE

t

AH

t

AS

A1

t

CEH

t

CES

BWE,

BW[A :D]

Data Out (Q)

High-Z

ADV

BURST READ BURST WRITE

D(A2) D(A2 + 1) D(A2 + 1)

D(A1)

D(A3) D(A3 + 1) D(A3 + 2)D(A2 + 3)

A2 A3

Data In (D)

Extended BURST WRITE

D(A2 + 2)

Single WRITE

t

ADH

t

ADS

t

ADH

t

ADS

t

OEHZ

t

ADVH

t

ADVS

t

WEH

t

WES

t

DH

t

DS

GW

t

WEH

t

WES

Byte write signals are

ignored for first cycle when

ADSP initiates burst

ADSC extends burst

ADV suspends burst

DON’T CARE

UNDEFINED

Notes

22. On this diagram, when CE

is LOW, CE

1

is LOW, CE

2

is HIGH and CE

3

is LOW. When CE is HIGH, CE

1

is HIGH or CE

2

is LOW or CE

3

is HIGH.

23.

Full width Write can be initiated by either GW

LOW; or by GW HIGH, BWE LOW and BW

[A:D]

LOW.

1 2 ... 17 18 19 20 21 22 23 24 25 26 27 28 29 30

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