Cypress Semiconductor enCoRe CY7C601xx Uživatelská příručka stáhnout pdf (Strana 47)

CY7C601xx

CY7C602xx

Document 38-16016 Rev. *C Page 47 of 62

Figure 14. Timer Functional Timing Diagram

Table 78.Programmable Interval Reload Low (PIRL) [0x28] [R/W]

Bit # 7 6 5 4 3 2 1 0

Field Prog Interval [7:0]

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 000 0

Bit [7:0]: Prog Interval [7:0]

This register holds the lower 8 bits of the timer. While writing into the 12-bit reload register, write lower byte first then the higher nibble.

Table 79.Programmable Interval Reload High (PIRH) [0x29] [R/W]

Bit # 7 6 5 4 3 2 1 0

Field Reserved Prog Interval[11:8]

Read/Write -- -- -- -- R/W R/W R/W R/W

Default 0 0 0 0 000 0

Bit [7:4]: Reserved

Bit [3:0]: Prog Interval [11:8]

This register holds the higher 4 bits of the timer. While writing into the 12-bit reload register, write lower byte first then the higher

nibble.

clk_captimer

16-bit free

running counter

clk_sys

capture0

cap0_rise

cap0_fall

cap1_rise

cap1_fall

cap0_rise_reg

cap0_fall_reg

cap1_fall_reg

cap1_rise_reg

cap1_fall_reg

cap1_rise_reg

capture1

Timing diagrams when cap0 is in 8 bit mode

Timing diagrams when cap0 is in 16 bit mode

1 2 ... 42 43 44 45 46 47 48 49 50 51 52 ... 61 62

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Cypress Semiconductor enCoRe CY7C601xx Uživatelská příručka Strana 47