Cypress Semiconductor enCoRe CY7C601xx Uživatelská příručka stáhnout pdf (Strana 39)

CY7C601xx

CY7C602xx

Document 38-16016 Rev. *C Page 39 of 62

P2 Configuration

P3 Configuration

P4 Configuration

Table 60.P2 Configuration (P2CR) [0x15] [R/W]

Bit # 7 6 5 4 3 2 1 0

Field Reserved Int Enable Int Act Low TTL Thresh High Sink Open Drain Pull Up Enable Output Enable

Read/Write –R/WR/WR/WR/W R/W R/W R/W

Default 00000000

In CY7C602xx this register controls the operation of pins P2.0–P2.1. In the CY7C601xx, this register controls the operation of

pins P2.0–P2.7.

The 50-mA sink drive capability is only available on pin P2.7 and only on the CY7C601xx. In the CY7C602xx, only 8-mA sink

drive capability is available on this pin regardless of the setting of the High Sink bit.

Table 61.P3 Configuration (P3CR) [0x16] [R/W]

Bit # 7 6 5 4 3 2 1 0

Field Reserved Int Enable Int Act Low TTL Thresh High Sink Open Drain Pull Up Enable Output Enable

Read/Write –R/WR/WR/WR/W R/W R/W R/W

Default 00000000

In CY7C602xx this register controls the operation of pins P3.0–P3.1. In the CY7C601xx, this register controls the operation of

pins P3.0–P3.7.

The 50-mA sink drive capability is only available on pin P3.7 and only on the CY7C601xx. In the CY7C602xx, only 8-mA sink

drive capability is available on this pin regardless of the setting of the High Sink bit.

Table 62.P4 Configuration (P4CR) [0x17] [R/W]

Bit # 7 6 5 4 3 2 1 0

Field Reserved Int Enable Int Act Low TTL Thresh High Sink Open Drain Pull Up Enable Output Enable

Read/Write – R/W R/W R/W R/W R/W R/W R/W

Default 0 0 0 0 0 0 0 0

This register exists only in the CY7C601xx. This register controls the operation of pins P4.0–P4.3.

1 2 ... 34 35 36 37 38 39 40 41 42 43 44 ... 61 62

Žádné komentáře

Cypress Semiconductor enCoRe CY7C601xx Uživatelská příručka Strana 39