Cypress Semiconductor SL811HS Specifikace stáhnout pdf (Strana 25)

SL811HS

Document #: 38-08008 Rev. *A Page 25 of 29

7.6.2 I/O Read Cycle

Note. NCS can be kept LOW during multiple Read cycles provided nRD is cycled. Rd Cycle Time for Auto Inc Mode Reads is

150 ns minimum.

Parameter Description Min. Typ. Max.

Write pulse width 65 ns

Read pulse width 65 ns

WCSU

Chip select set-up to nWR 0 ns

WASU

A0 address set-up time 65 ns

WAHLD

A0 address hold time 10 ns

WDSU

Data to Write HIGH set-up time 60 ns

WDHLD

Data hold time after Write HIGH 5 ns

RACC

Data valid after Read LOW 20 ns 25 ns

RDHLD

Data hold after Read HIGH 5 ns

RCSU

Chip select LOW to Read LOW 0 ns

RSHLD

NCS hold after Read HIGH 0 ns

CSCS

* nCS inactive to nCS *asserted 85 ns

WRRDL

nWR HIGH to nRD LOW 85ns

nRD

D0-D7

DATA

twr

twahld

twdhld

twasu

twdsu

trdhld

I/O Read Cycle from Register or Memory Buffer

Address

trdp

nWR

trshld

trcsu

nCS

tracc

Tcscs *Note

twrrdl

1 2 ... 20 21 22 23 24 25 26 27 28 29

SL811HS 1
License Agreement 3
1.0 Conventions 4
2.0 Definitions 4
3.0 References 4
4.0 Introduction 4
Master/Slave 5
Controller 5
4.5 Interrupt Controller 6
4.6 Buffer Memory 6
4.7 PLL Clock Generator 6
5.0 SL811HS Registers 8
5.2 USB Control Registers 9
5.3 SL811HS Control Registers 12
SL811HSH 16
99''  18
Y1 &7  18
SL811HST 19
SL811HST 21
YYWW-X.X 21
XXXX 21
7.1 Absolute Maximum Ratings 22
RESET TIMING 26
CLOCK TIMING 27
8.0 Package Diagrams 28
28-pin PLCC 28
48-pin TQFP 28

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