Cypress Semiconductor CYV15G0404DXB Uživatelská příručka stáhnout pdf (Strana 3)

CYV15G0404DXB Evaluation Board

Users Guide

Page 3 of 56

LIST OF FIGURES

Figure 4-1. CYV15G0404DXB Block Diagram ........................................................................................6

Figure 4-2. Transmit Path Block Diagram................................................................................................7

Figure 4-3. Receive Path Block Diagram................................................................................................. 8

Figure 4-4. Device Configuration Control Block Diagram........................................................................9

Figure 5-1. Photograph of Board with Numbering of Connectors..........................................................10

Figure 5-2. Channel A Connectors ........................................................................................................11

Figure 5-3. Optical Interface Signals .....................................................................................................13

Figure 5-4. JTAG Interface Signals .......................................................................................................13

Figure 6-1. Speed Select Control with Jumpers ....................................................................................17

Figure 6-2. Controlling Dip Switch Settings ...........................................................................................17

Figure 6-3. Write Enable and Reset Buttons ......................................................................................... 17

Figure 6-4. Top View of REFCLK Connectors.......................................................................................18

Figure 7-1. BIST Mode Operation.......................................................................................................... 19

Figure 7-2. Pictorial Representation of the Internal BIST Set-up...........................................................20

Figure 7-3. The Eye Diagram through the Signal Analyzer ...................................................................21

Figure 7-4. SMA Connectors for External Loopback Mode ...................................................................22

Figure 7-5. Loop Enable, Use Local Clock, and Input Select DIP Switches..........................................22

Figure 7-6. Optical Connector for External Loopback Mode..................................................................22

Figure 7-7. Loop Enable, Use Local Clock, and Input Select DIP Switches..........................................22

Figure 7-8. Generated Clock, Data and Control Signals for Encoded Mode from DG2020 ..................24

Figure 7-9. Generated Clock and Data Signals for Encoder Bypass Mode from DG2020....................25

Figure 7-10. Pictorial Representation of the Reclocker Test Equipment Set-up ...................................28

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Cypress Semiconductor CYV15G0404DXB Uživatelská příručka Strana 3