Cypress Semiconductor CYV15G0404DXB Uživatelská příručka stáhnout pdf (Strana 12)

CYV15G0404DXB Evaluation Board

Users Guide

Page 12 of 56

J12x REFCLKx- SMA Connector for REFCLKx -

• Negative input of reference clock for channel x

J13x, J14x SERINx1+, SERINx1- SMA Connectors for serial data input of channel x

• PECL compatible primary differential serial data inputs

• Routed through 50-Ohm impedance

• AC coupling capacitors present

• 100-Ohm differential load present

J15x, J16x SEROUTx1-,

SEROUTx1+

SMA Connectors for serial data output of channel x

• PECL-compatible primary differential serial data CML outputs

• Routed through 50-Ohm impedance

• AC coupling capacitors present

• Expects to see a 50-Ohm single ended or 100-Ohm differential termination in

the receive ends

J17x RXCLKx+ SMA Connector for RXCLKx

• Recovered clock at the receiver for channel x

J18x REFCLKx+

Headers to probe the reference clock for channel x

J19x LFIx Header to probe the Link Fault Indicator status for channel x

J25 OPT LVTTL Output

• Headers to probe the signals for the optical modules

• Control Signals: OPT_RATE_SEL, OPT_TX_DISABLE

• Output Signals: OPT_TX_FAULT_x, OPT_LOS_x (x = A,B,C,D)

J26 ADDR[3:0] Headers to control the configuration addressing bus or to probe the ADDR[3:0]

dip switches

J27 LPENx Header to control Loop Enable signal or probe the LPEN dip switch for channel x

J28 INSELx Header to control the Receive Input Selector or probe the INSEL dip switch for

channel x

J29 ULCx

Header to control the Use Local Clock signal or probe the ULC dip switch for

channel x

J30 DATA[7:0] Headers to control the configuration data bus or probe the DATA[7:0] dip switches

J1 RCLKENx Header to control the Reclocker Enable signal or probe the RCLKEN dip switch

for channel x

XT1x Optical Modules Option for Small Form-Factor Pluggable (SFP) optical modules.

The optical modules make use of the secondary input (INx2+

) and secondary

output (OUTx2+

) in each transceiver channel.

D1x LFIx

asynchronous

• Link Fault Indication output LEDs

• Signal active LOW. LED is lit when signal is active.

• Logical OR of six internal conditions:

— Received serial data frequency outside expected range

— Analog amplitude below expected levels

— Transition density lower than expected

— Receive channel disabled

—ULCx

is LOW

— Absence of REFCLKx±

Y1x REFCLK± 14-pin DIP socket for an external Crystal Oscillator to provide an independent

reference clock for channel x.

Table 5-1. Description of Connectors of the CYV15G0404DXB Evaluation Board (continued)

Connectors Signals Description

[+] Feedback

1 2 ... 7 8 9 10 11 12 13 14 15 16 17 ... 56 57

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