Cypress Semiconductor Perform CY7C1513KV18 Uživatelský manuál stáhnout pdf (Strana 17)

CYWUSB6934

CYWUSB6932

Document Number : 38-16007 Rev. *L Page 17 of 34

Note

7. The Valid bit in the Transmit SERDES Valid register (Reg 0x10) is used to mark whether the radio will send data or preamble during that bit time of the data byte.

Data is sent LSB first. The SERDES will continue to send data until there are no more VALID bits in the shifter. For example, writing 0x0F to the Transmit SERDES

Valid register (Reg 0x10) will send half a byte.

Table 16. Transmit SERDES Data

Addr: 0x0F REG_TX_DATA Default: 0x00

76543210

Data

Bit Name Description

7:0 Data Transmit Data. The over-the-air transmitted order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed

by bit 4, followed by bit 5, followed by bit 6, followed by bit 7.

Table 17. Transmit SERDES Valid

Addr: 0x10 REG_TX_VALID Default: 0x00

76543210

Valid

Bit Name Description

7:0 Valid

[7]

The Valid bits are used to determine which of the bits in the Transmit SERDES Data register (reg 0x0F) are valid.

1 = Valid transmit bit.

0 = Invalid transmit bit.

Table 18. PN Code

Addr: 0x11-18

REG_PN_CODE

Default:

0x1E8B6A3DE0E9B222

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

Address 0x18 Address 0x17 Address 0x16 Address 0x15

313029282726252423222120191817161514131211109876543210

Address 0x14 Address 0x13 Address 0x12 Address 0x11

Bit Name Description

63:0 PN Codes The value inside the 8 byte PN code register is used as the spreading code for DSSS communication. All 8 bytes

can be used together for 64 chips/bit PN code communication, or the registers can be split into two sets of 32

chips/bit PN codes and these can be used alone or with each other to accomplish faster data rates. Not any 64

chips/bit value can be used as a PN code as there are certain characteristics that are needed to minimize the

possibility of multiple PN codes interfering with each other or the possibility of invalid correlation. The over-the-air

order is bit 0 followed by bit 1... followed by bit 62, followed by bit 63.

Not Recommended for New Designs

[+] Feedback

1 2 ... 12 13 14 15 16 17 18 19 20 21 22 ... 33 34

Komentáře k této Příručce

Žádné komentáře

Cypress Semiconductor Perform CY7C1513KV18 Uživatelský manuál Strana 17

Komentáře k této Příručce

Související produkty a manuály pro ne Cypress Semiconductor Perform CY7C1513KV18