
Document Number : 38-16007 Rev. *L Page 5 of 34
Table 2. SPI Transaction Format
Byte 1 Byte 1+N
Bit # 7 6 [5:0] [7:0]
Bit Name DIR INC Address Data
Figure 1. SPI Single Read Sequence
Figure 2. SPI Burst Read Sequence
Figure 3. SPI Single Write Sequence
Figure 4. SPI Burst Write Sequence
SS
MOSI
MISO
SCK
DIR INC
A0A1A2A3A4A5
D0D1D2D3D4D5
D6D7
data to mcu
addrcmd
00
SS
MOSI
MISO
SCK
A0A1A2A3A4A5
D0D1D2D3D4D5
D6D7
D0D1D2D3D4D5
D6D7
data to mcu
1
data to mcu
1+N
addrcmd
DIR INC
01
SS
MOSI
MISO
SCK
DIR INC
A0A1A2A3A4A5
D0D1D2D3D4D5
D6D7
data from mcu
addrcmd
10
SS
MOSI
MISO
SCK
A0A1A2A3A4A5
D0D1D2D3D4D5
D6D7
D0D1D2D3D4D5
D6D7
data from mcu
1
data from mcu
1+N
addrcmd
DIR INC
11
Not Recommended for New Designs
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