Cypress Semiconductor NoBL CY7C1472V33 Uživatelská příručka Strana 1

ZestSC1 User Guide Author Charles Sweeney and Matt Bowen Version 1.06 Date 4th December 2007 Orange Tree Technologies

Orange Tree Technologies Page 10 of 57 J6 Power source Connect Pins Power Source 1-2 Power jack J5 or USB 2-3 Hard disk drive connector J7 J7

ZestSC1 User Guide CONFIDENTIAL Page 11 of 57 7 Description The block diagram of ZestSC1 is shown in Figure 3. It is a desktop board with a Xili

Orange Tree Technologies Page 12 of 57 the FIFO interface. The FIFO interface can be controlled by either an internal master in the FX2 or an extern

ZestSC1 User Guide CONFIDENTIAL Page 13 of 57 The GPIF also has 6 Ready input signals and 6 Control output signals for general purpose use, and t

Orange Tree Technologies Page 14 of 57 7.1.1.1 FPGA Configuration The GPIF mode is used for configuring the FPGA using the SelectMap port. The FX2

ZestSC1 User Guide CONFIDENTIAL Page 15 of 57 reversing the data flow, select a large value (256 or greater). For applications which alternate t

Orange Tree Technologies Page 16 of 57 7.1.1.3 Register Reads and Writes The FX2 external bus is connected to the FPGA allowing memory mapped acces

ZestSC1 User Guide CONFIDENTIAL Page 17 of 57 Figure 6. Register read and write accesses 7.1.1.4 User Signals The 8 user signals between the F

Orange Tree Technologies Page 18 of 57 • I/O – 49 I/O signals, 2 of which can be a differential pair clock input. The I/O signals FPGA banks have 5

ZestSC1 User Guide CONFIDENTIAL Page 19 of 57 USER_SRAM_A: in std_logic_vector(22 downto 0); -- 23-bit address USER_SRAM_W: in std_logic;

Orange Tree Technologies Page 2 of 57 Version Date Comment 1.00 02/11/04 First Version 1.01 01/02/05 Clarifications for power supply and clock

Orange Tree Technologies Page 20 of 57 the data by 2 further clocks as required by the ZBT SRAM. Byte write strobes are not implemented. For read cy

ZestSC1 User Guide CONFIDENTIAL Page 21 of 57 power switch so is available only after the FX2 has enabled the power switch using its Port E bit 0

Orange Tree Technologies Page 22 of 57 Figure 8. Approximate Positions of LEDs 7.6 Clocks The FPGA has two fixed frequency clock inputs of 48MHz

ZestSC1 User Guide CONFIDENTIAL Page 23 of 57 2.5W (500mA @ nominal 5V) is available from USB. The following table shows the typical quiescent po

Orange Tree Technologies Page 24 of 57 7.8 Build Options The following modifications can be made to the board by arrangement with Orange Tree Techn

ZestSC1 User Guide CONFIDENTIAL Page 25 of 57 8 Using the Host Library The ZestSC1 host support software consists of a system driver and a host

Orange Tree Technologies Page 26 of 57 9 Host Utilities A number of utilities are provided with the ZestSC1 support library. These can be found in

ZestSC1 User Guide CONFIDENTIAL Page 27 of 57 10 Examples The ZestSC1 Support package contains a number of examples to illustrate the use of the

Orange Tree Technologies Page 28 of 57 11 Host Library Function Reference ZestSC1CountCards ZESTSC1_STATUS ZestSC1CountCards( unsigned long *NumCa

ZestSC1 User Guide CONFIDENTIAL Page 29 of 57 unsigned long NumCards; unsigned long *CardIDs; /* Get the number of cards in the system */ ZestSC

ZestSC1 User Guide CONFIDENTIAL Page 3 of 57 1 Contents 1 CONTENTS...

Orange Tree Technologies Page 30 of 57 ZestSC1OpenCard ZESTSC1_STATUS ZestSC1OpenCard( unsigned long CardID, ZESTSC1_HANDLE *Handle); Parameters

ZestSC1 User Guide CONFIDENTIAL Page 31 of 57 ZestSC1GetCardInfo ZESTSC1_STATUS ZestSC1GetCardInfo( ZESTSC1_HANDLE Handle, ZESTSC1_CARD_INFO *In

Orange Tree Technologies Page 32 of 57 ZESTSC1_CARD_INFO Info; /* Open a card with ID of 1 */ ZestSC1OpenCard(1, &Handle); /* Obtain informati

ZestSC1 User Guide CONFIDENTIAL Page 33 of 57 ZestSC1SetTimeOut ZESTSC1_STATUS ZestSC1SetTimeOut( ZESTSC1_HANDLE Handle, unsigned long MilliSeco

Orange Tree Technologies Page 34 of 57 ZestSC1SetCardID ZESTSC1_STATUS ZestSC1SetCardID( ZESTSC1_HANDLE Handle, unsigned long CardID); Parameters

ZestSC1 User Guide CONFIDENTIAL Page 35 of 57 ZestSC1CloseCard ZESTSC1_STATUS ZestSC1CloseCard(ZESTSC1_HANDLE Handle); Parameters Handle Hand

Orange Tree Technologies Page 36 of 57 ZestSC1RegisterErrorHandler ZESTSC1_STATUS ZestSC1RegisterErrorHandler( ZESTSC1_ERROR_FUNC Function); Param

ZestSC1 User Guide CONFIDENTIAL Page 37 of 57 /* Other calls to ZestSC1 library here */ /* Note that the return code need not be checked as Er

Orange Tree Technologies Page 38 of 57 ZestSC1GetErrorMessage ZESTSC1_STATUS ZestSC1GetErrorMessage(ZESTSC1_STATUS Status, char **Buffer); Paramet

ZestSC1 User Guide CONFIDENTIAL Page 39 of 57 ZestSC1ConfigureFromFile ZESTSC1_STATUS ZestSC1ConfigureFromFile(ZESTSC1_HANDLE Handle, char *File

Orange Tree Technologies Page 4 of 57 2 Glossary DCI Digitally Controlled Impedance DCM Digital Clock Manager Endpoint A USB endpoint is the

Orange Tree Technologies Page 40 of 57 Configuring the FPGA with an incorrect BIT file can damage your hardware. Ensure that FPGA pins are connect

ZestSC1 User Guide CONFIDENTIAL Page 41 of 57 ZestSC1LoadFile ZESTSC1_STATUS ZestSC1LoadFile( char *FileName, ZESTSC1_IMAGE *Image); Parameter

Orange Tree Technologies Page 42 of 57 /* Other execution operations here */ /* Configure the FPGA from the image */ ZestSC1Configure(Handle, Imag

ZestSC1 User Guide CONFIDENTIAL Page 43 of 57 ZestSC1Configure ZESTSC1_STATUS ZestSC1Configure( ZESTSC1_HANDLE Handle, ZESTSC1_IMAGE Image); P

Orange Tree Technologies Page 44 of 57 /* Register the FPGA configuration image */ ZestSC1RegisterImage(Buffer, Length, &Image); /* Other init

ZestSC1 User Guide CONFIDENTIAL Page 45 of 57 ZestSC1RegisterImage ZESTSC1_STATUS ZestSC1RegisterImage(void *Buffer, unsigned long BufferLength,

Orange Tree Technologies Page 46 of 57 /* Open a card with ID of 1 */ ZestSC1OpenCard(1, &Handle); /* Other execution operations here */ /* C

ZestSC1 User Guide CONFIDENTIAL Page 47 of 57 ZestSC1FreeImage ZESTSC1_STATUS ZestSC1FreeImage(ZESTSC1_IMAGE Image); Parameters Image FPGA co

Orange Tree Technologies Page 48 of 57 ZestSC1ReadRegister ZESTSC1_STATUS ZestSC1ReadRegister( ZESTSC1_HANDLE Handle, unsigned long Offset, unsign

ZestSC1 User Guide CONFIDENTIAL Page 49 of 57 ZestSC1WriteRegister ZESTSC1_STATUS ZestSC1WriteRegister( ZESTSC1_HANDLE Handle, unsigned long Of

ZestSC1 User Guide CONFIDENTIAL Page 5 of 57 4 Introduction Thank you for purchasing a ZestSC1. This user guide explains how to install the Zest

Orange Tree Technologies Page 50 of 57 ZestSC1ReadData ZESTSC1_STATUS ZestSC1ReadData( ZESTSC1_HANDLE Handle, void *Buffer, unsigned long Le

ZestSC1 User Guide CONFIDENTIAL Page 51 of 57 ZestSC1WriteData ZESTSC1_STATUS ZestSC1WriteData( ZESTSC1_HANDLE Handle, void *Buffer, unsigned l

Orange Tree Technologies Page 52 of 57 ZestSC1SetSignalDirection ZESTSC1_STATUS ZestSC1SetSignalDirection(ZESTSC1_HANDLE Handle, unsigned char Dire

ZestSC1 User Guide CONFIDENTIAL Page 53 of 57 /* Configure the FPGA */ ZestSC1ConfigureFromFile(Handle, “example.bit”); /* Set the signal to ‘a

Orange Tree Technologies Page 54 of 57 ZestSC1SetSignals ZESTSC1_STATUS ZestSC1SetSignals( ZESTSC1_HANDLE Handle, unsigned char Value); Parameter

ZestSC1 User Guide CONFIDENTIAL Page 55 of 57 /* Set the signal to ‘active’ */ ZestSC1SetSignals(Handle, 1); /* Set the signal to ‘inactive’ */

Orange Tree Technologies Page 56 of 57 ZestSC1ReadSignals ZESTSC1_STATUS ZestSC1ReadSignals( ZESTSC1_HANDLE Handle, unsigned char *Value); Paramet

ZestSC1 User Guide CONFIDENTIAL Page 57 of 57 ZestSC1WaitForInterrupt ZESTSC1_STATUS ZestSC1WaitForInterrupt(ZESTSC1_HANDLE Handle); Parameters

Orange Tree Technologies Page 6 of 57 6 Installation 6.1 Packing List Please check that the following items are in the package sent to you and con

ZestSC1 User Guide CONFIDENTIAL Page 7 of 57 standoffs in a position where it cannot touch any other items such as chassis, boards or cables. 7.

Orange Tree Technologies Page 8 of 57 Unless otherwise stated, pin 1 is indicated on the PCB by the figure ‘1’. J1 USB B connector J2 Test header

ZestSC1 User Guide CONFIDENTIAL Page 9 of 57 J4 User I/O Header IO pins are connected directly to the FPGA. See UCF for FPGA pin connections.