Cypress Semiconductor enCoRe CY7C604XX Uživatelský manuál stáhnout pdf (Strana 24)

CY7C603xx

Document #: 38-16018 Rev. *D Page 24 of 29

AC Programming Specifications

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V

and 0°C <

< 70°C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25°C and are for design guidance only.

Table 26.2.7V AC External Clock Specifications

Parameter Description Min. Typ. Max. Unit Notes

OSCEXT

Frequency with CPU Clock divide by 1 0.093 –3.08

MHz Maximum CPU frequency is 3 MHz at 2.7V.

With the CPU clock divider set to 1, the

external clock must adhere to the maximum

frequency and duty cycle requirements.

OSCEXT

Frequency with CPU Clock divide by 2 or

greater

0.186 – 6.35 MHz If the frequency of the external clock is

greater than 3 MHz, the CPU clock divider

must be set to 2 or greater. In this case, the

CPU clock divider will ensure that the fifty

percent duty cycle requirement is met.

– High Period with CPU Clock divide by 1 160 – 5300 ns

– Low Period with CPU Clock divide by 1 160

– –ns

– Power Up IMO to Switch 150

– – Ps

Table 27.AC Programming Specifications

Parameter Description Min. Typ. Max. Unit Notes

RSCLK

Rise Time of SCLK 1 – 20 ns

FSCLK

Fall Time of SCLK 1 – 20 ns

SSCLK

Data Set up Time to Falling Edge of SCLK 40 – – ns

HSCLK

Data Hold Time from Falling Edge of SCLK 40 – – ns

SCLK

Frequency of SCLK 0 – 8 MHz

ERASEB

Flash Erase Time (Block) – 15 – ms

WRITE

Flash Block Write Time – 30 – ms

DSCLK3

Data Out Delay from Falling Edge of SCLK – – 50 ns 3.0 d Vdd d 3.6

DSCLK2

Data Out Delay from Falling Edge of SCLK – – 70 ns 2.4 d Vdd d 3.0

1 2 ... 19 20 21 22 23 24 25 26 27 28 29

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