
Document #: 001-01638 Rev. *H Page 5 of 29
Pin Definitions
Left Port Right Port Description
CE
L
CE
R
Chip enable
R/W
L
R/W
R
Read/write enable
OE
L
OE
R
Output enable
A
0L
–A
13L
A
0R
–A
13R
Address (A
0
–A
11
for 4k devices; A
0
–A
12
for 8k devices; A
0
–A
13
for 16k devices).
I/O
0L
–I/O
15L
I/O
0R
–I/O
15R
Data bus input/output for x16 devices; I/O
0
–I/O
7
for x8 devices.
SEM
L
SEM
R
Semaphore enable
UB
L
UB
R
Upper byte select (I/O
8
–I/O
15
for x16 devices; Not applicable for x8 devices).
LB
L
LB
R
Lower byte select (I/O
0
–I/O
7
for x16 devices; Not applicable for x8 devices).
INT
L
INT
R
Interrupt flag
BUSY
L
BUSY
R
Busy flag
IRR0, IRR1 Input read register (IRR) for CYDC128B16.
ODR0-ODR4 Output drive register; these outputs are Open Drain.
SFEN
Special function enable
M/S
Master or slave select
V
CC
Core power
GND Ground
V
DDIOL
Left port I/O voltage
V
DDIOR
Right port I/O voltage
NC No connect. Leave this pin unconnected.
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