Cypress Semiconductor CY7C1473BV33 Uživatelský manuál stáhnout pdf (Strana 7)

CY7C1471BV33

CY7C1473BV33

Document Number: 001-15029 Rev. *G Page 7 of 31

Pin Definitions

Name I/O Description

, A

, A Input-

Synchronous

Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK.

[1:0]

is fed to the two-bit burst counter.

, BW

Input-

Synchronous

Byte write inputs, active LOW. Qualified with

WE to conduct writes to the SRAM. Sampled on the rising

edge of CLK.

WE Input-

Synchronous

Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal

must be asserted LOW to initiate a write sequence.

ADV/LD Input-

Synchronous

Advance/load input. Advances the on-chip address counter or loads a new address. When HIGH (and

CEN

is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded

into the device for an access. After deselection, drive ADV/LD

LOW to load a new address.

CLK Input-

Clock

Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN

. CLK is

only recognized if CEN

is active LOW.

Input-

Synchronous

Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE

and CE

to select or deselect the device.

Input-

Synchronous

Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE

and CE

to select or deselect the device.

Input-

Synchronous

Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE

and

to select or deselect the device.

Input-

Asynchronous

Output enable, asynchronous input, active LOW. Combined with the synchronous logic block inside

the device to control the direction of the I/O pins. When LOW, the I/O pins are enabled to behave as

outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during

the data portion of a write sequence, during the first clock when emerging from a deselected state, and

when the device is deselected.

CEN

Input-

Synchronous

Clock enable input, active LOW. When asserted LOW the clock signal is recognized by the SRAM.

When deasserted HIGH the clock signal is masked. Because deasserting CEN

does not deselect the

device, CEN

can be used to extend the previous cycle when required.

ZZ Input-

Asynchronous

ZZ “Sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition with

data integrity preserved. During normal operation, this pin must be LOW or left floating. ZZ pin has an

internal pull-down.

I/O-

Synchronous

Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the

rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the

addresses presented during the previous

clock rise of the

read cycle. The direction of the pins is

controlled by OE

. When OE is asserted LOW, the

pins behave as outputs. When HIGH, DQ

and DQP

are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion of a

write sequence, during the first clock when emerging from a deselected state, and when the device is

deselected, regardless of the state of OE

DQP

I/O-

Synchronous

Bidirectional data parity I/O lines. Functionally, these signals are identical to DQ

During write

sequences, DQP

is controlled by BW

correspondingly.

MODE Input Strap

Mode input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence.

When tied to V

or left floating selects interleaved burst sequence.

Power Supply Power supply inputs to the core of the device.

DDQ

I/O Power

Supply

Power supply for the I/O circuitry.

Ground Ground for the device.

TDO JTAG serial

output

Synchronous

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is

not used, this pin must be left unconnected. This pin is not available on TQFP packages.

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