Cypress Semiconductor CY7C1383D Uživatelský manuál stáhnout pdf (Strana 7)

CY7C1381D

CY7C1383D

Document #: 38-05544 Rev. *C Page 7 of 29

Functional Overview

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. Maximum access delay from

the clock rise (t

CDV

) is 6.5 ns (133-MHz device).

The CY7C1381D/CY7C1383D supports secondary cache in

systems utilizing either a linear or interleaved burst sequence.

The interleaved burst order supports Pentium and i486™

processors. The linear burst sequence is suited for processors

that utilize a linear burst sequence. The burst order is

user-selectable, and is determined by sampling the MODE

input. Accesses can be initiated with either the Processor

Address Strobe (ADSP

) or the Controller Address Strobe

(ADSC

). Address advancement through the burst sequence is

controlled by the ADV input. A two-bit on-chip wraparound

burst counter captures the first address in a burst sequence

and automatically increments the address for the rest of the

burst access.

Byte write operations are qualified with the Byte Write Enable

(BW

) and Byte Write Select (BWX) inputs. A Global Write

Enable (GW

) overrides all byte write inputs and writes data to

all four bytes. All writes are simplified with on-chip

synchronous self-timed write circuitry.

Three synchronous Chip Selects (CE

, CE

[2]

) and an

asynchronous Output Enable (OE

) provide for easy bank

selection and output tri-state control. ADSP

is ignored if CE

is HIGH.

Single Read Accesses

A single read access is initiated when the following conditions

are satisfied at clock rise: (1) CE

, CE

, and CE

[2]

are all

asserted active, and (2) ADSP

or ADSC is asserted LOW (if

the access is initiated by ADSC

, the write inputs must be

deasserted during this first cycle). The address presented to

the address inputs is latched into the address register and the

burst counter/control logic and presented to the memory core.

If the OE input is asserted LOW, the requested data will be

available at the data outputs a maximum to t

CDV

after clock

rise. ADSP

is ignored if CE

is HIGH.

Single Write Accesses Initiated by ADSP

This access is initiated when the following conditions are

satisfied at clock rise: (1) CE

, CE

[2]

are all asserted

active, and (2) ADSP

is asserted LOW. The addresses

presented are loaded into the address register and the burst

inputs (GW

, BW

, and BW

)are ignored during this first clock

cycle. If the write inputs are asserted active (see Write Cycle

Descriptions table for appropriate states that indicate a write)

on the next clock rise, the appropriate data will be latched and

written into the device. Byte writes are allowed. All I/Os are

tri-stated during a byte write.Since this is a common I/O

device, the asynchronous OE

input signal must be deasserted

and the I/Os must be tri-stated prior to the presentation of data

to DQs. As a safety precaution, the data lines are tri-stated

once a write cycle is detected, regardless of the state of OE

Single Write Accesses Initiated by ADSC

This write access is initiated when the following conditions are

satisfied at clock rise: (1) CE

, CE

, and CE

[2]

are all asserted

active, (2) ADSC

is asserted LOW, (3) ADSP is deasserted

HIGH, and (4) the write input signals (GW

, BWE, and BW

)

indicate a write access. ADSC

is ignored if ADSP is active

LOW.

The addresses presented are loaded into the address register

and the burst counter/control logic and delivered to the

memory core. The information presented to DQ

[A:D]

will be

written into the specified address location. Byte writes are

allowed. All I/Os are tri-stated when a write is detected, even

a byte write. Since this is a common I/O device, the

asynchronous OE

input signal must be deasserted and the

I/Os must be tri-stated prior to the presentation of data to DQ

As a safety precaution, the data lines are tri-stated once a write

cycle is detected, regardless of the state of OE

Burst Sequences

The CY7C1381D/CY7C1383D provides an on-chip two-bit

wraparound burst counter inside the SRAM. The burst counter

is fed by A

[1:0]

, and can follow either a linear or interleaved

burst order. The burst order is determined by the state of the

MODE input. A LOW on MODE will select a linear burst

sequence. A HIGH on MODE will select an interleaved burst

SSQ

I/O Ground Ground for the I/O circuitry.

TDO JTAG serial output

Synchronous

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the

JTAG feature is not being utilized, this pin should be left unconnected. This pin is not

available on TQFP packages.

TDI JTAG serial input

Synchronous

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature

is not being utilized, this pin can be left floating or connected to V

through a pull up

resistor. This pin is not available on TQFP packages.

TMS JTAG serial input

Synchronous

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature

is not being utilized, this pin can be disconnected or connected to V

. This pin is not

available on TQFP packages.

TCK JTAG-

Clock

Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must

be connected to V

. This pin is not available on TQFP packages.

NC – No Connects. Not internally connected to the die. 36M, 72M, 144M, 288M, 576M and 1G

are address expansion pins and are not internally connected to the die.

/DNU Ground/DNU This pin can be connected to Ground or should be left floating.

Pin Definitions (continued)

Name I/O Description

1 2 3 4 5 6 7 8 9 10 11 12 ... 28 29

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