Cypress Semiconductor SL811HS Uživatelský manuál stáhnout pdf (Strana 3)

Interfacing an External Processor to the SL811HS/S

Example SL811HS/S Circuits

Two typical circuit configurations are shown in Figures 5 and

6. The 48-pin version of the SL811HS is shown in each of the

figures; however the same pin configurations apply to the 28-

pin package. Figure 5 represents a typical USB embedded

host with power protection and all associated components.

The clock may be supplied from a 3.3-volt 12-/48-MHz CMOS

oscillator or a 12-/48-MHz crystal. The chosen clock source

must meet the jitter and accuracy requirements of the USB

2.0 specification, meaning that driving the clock from an ex-

ternal processor timer/counter output may or may not be pos-

sible. Reset is generated via a GPIO on the embedded pro-

cessor. Reset could also be generated from a dedicated POR

circuit.

Figure 6 shows a typical USB peripheral configuration for the

SL811HS or SL811S (minus the M/S pin). In this situation the

USB data line pull-up resistor must be able to be disabled

while power is disconnected; therefore two GPIO are required

on the embedded processor. In Figure 4 the pull-up resistor

is connected to D+, meaning that the circuit is configured for

full-speed USB operation. If low-speed USB operation is de-

sired, the pull up resistor should be connected to the D– sig-

nal. Total capacitance on the USB Vbus must be below 10 µF

to meet the USB 2.0 specification. A voltage regulator that

converts the Vbus 5 volts to 3.3 volts is not shown in the

schematic, but may be required if the device is bus powered.

nCS

nWR

nRD

D[7:0]

ADDR DATA @ ADDR

Figure 4. Example Read Transaction (not to scale)

Figure 5. SL811HS in a Typical USB Host Configuration

1 2 3 4

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Cypress Semiconductor SL811HS Uživatelský manuál Strana 3