Cypress Semiconductor SL811HS Uživatelský manuál stáhnout pdf (Strana 2)

Interfacing an External Processor to the SL811HS/S

external inverter may be required if a particular processor

does not support active HIGH interrupt signaling.

DATA BUS (D[7:0]) – The SL811HS/S bidirectional data bus

is used to transfer data in and out of registers or memory. The

data bus is normally held in a high-impedance state unless

both nCS and nRD are asserted during a read transaction.

The D[7:0] pins should be connected to the least significant

byte of the embedded processor’s data bus.

RESET (NRST) – Reset must be asserted LOW at power-on

by the embedded processor or an external POR circuit. NRST

is asserted for 16 clock cycles of the CLK signal. Further

transactions with the SL811HS/S should not take place be-

fore 16 cycles of CLK after NRST is deasserted.

ROLE (M/S) – This signal determines the operating role for

the SL811HS at the assertion of an external reset. At the as-

sertion of NRST the value of the M/S pin is latched into the

internal M/S register bit. If M/S is held LOW, the SL811HS

acts as a USB host. If M/S is held HIGH, the SL811HS is a

USB peripheral. During normal operation the M/S bit does not

have any effect on the operation of the SL811HS. The oper-

ating role of the SL811HS may be changed without external

reset by software running on the embedded processor that

changes the SL811HS internal M/S register bit.

DMA SIGNALS (nDACK, nDRQ) – These peripheral-only

DMA related signals are typically not used with an embedded

processor so they are not described here. Please see the

SL811HS/S data sheet for more details on nDACK and

NDRQ.

The SL811HS/S I/Os are 5-volt tolerant, but will only drive its

own I/Os to 3.3 volts. As long the embedded processor has

TTL or 3.3-volt CMOS level inputs the SL811HS/S interface

should not require voltage translation buffering.

Figure 2 shows a typical example of the connection of a

SL811HS/S to generic embedded processor bus.

Example Transactions

Two example transactions are shown in Figures 3 and 4.

Figure 3 shows a simple write transaction where a register or

memory location is being written to.

Figure 4 shows a simple read transaction of a register or

memory location.

32-bit Embedded Processor

D[31:0]

A[31:2]

CS#

RD#

WR#

INT

GPIO

GPIO(s)

SL811HS/S

D[7:0]

nCS

nRD

nWR

INTRQ

NRST

(Other)

(A2)

(D[7:0])

Figure 2. Example Connection of a 32-bit Embedded Processor to the SL811HS/S

nCS

nWR

nRD

D[7:0]

ADDR DATA @ ADDR

Figure 3. Example Write Transaction (not to scale)

1 2 3 4

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