Cypress Semiconductor Perform CY7C1372D Uživatelská příručka stáhnout pdf (Strana 63)

There are several constraints internal for the DCM and Block RAMs such as

INST "inst_clocks/Inst_aclk_dcm/dcm_inst" LOC = "DCM_X1Y0" ;

INST "inst_clocks/Inst_bclk_dcm/dcm_inst" LOC = "DCM_X2Y0" ;

Note: Do NOT delete these DCM constraints – some Xilinx die revisions of the chips

require it!

Here is a typical location constraint for a block RAM used in the A/D interface component.

INST "inst_dsp_emif_a/inst_ififo0/fifo_int/B12" LOC = "RAMB16_X0Y1" ;

Finally, area constraints are used for components to control where on the chip specific logic

components are placed. Not only does this tend to improve timing, it is required for incremental

design flow.

AREA_GROUP "AG_inst_adc0" RANGE = SLICE_X84Y71:SLICE_X91Y56 ;

INST "inst_adc0" AREA_GROUP = "AG_inst_adc0" ;

The example constraint is an area constraint for the A/D component.

6.1.6.3 Logic Utilization

The Framework logic has the following logic utilization in each chip. This is taken from the .MRP

file output by the Xilinx tools, which has additional information on the logic consumption.

Innovative Integration FrameWork Logic User Guide 63

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