Cypress Semiconductor enCoRe CY7C64215 Uživatelský manuál stáhnout pdf (Strana 7)

August 17, 2011 Document No. 001-15340 Rev. *A

AN6073

The CY7C64215 CPU uses an interrupt controller with up to

20 vectors. Flash locations 00h to 2Ch are dedicated to

PSoC interrupt vectors. Flash locations 40h to 64h are dedi-

cated to USB, I2C, and sleep timer interrupt vectors. Interrupt

latency is based on time for current instruction, time to

change program counter to interrupt address (10 cycles), and

time for LJMP instruction to execute (5 cycles).

Figure 5. Interrupt Vectors and Program Memory

Organization

Program Counter

The CY7C64x13 uses a 14-bit Program Counter that allows

access to 8 KB of PROM. The lower eight bits are incre-

mented as instructions are loaded onto it. The higher six bits

are incremented when an XPAGE instruction is executed,

i.e., the last instruction to be executed following a 256-byte

sequential code access is an XPAGE instruction.

The 16-bit program counter in the CY7C64215 allows direct

access to 16K of the FLASH space. This is actually two 8-bit

registers, PCH and PCL

Differences Between M8B and M8C Processor Cores

The M8B CPU core was used in Cypress legacy devices.

Since then we’ve moved to the M8C core, which is a newer

CPU core—better, faster, and with a more efficient instruction

set.

Some of the major changes between the M8B and M8C are

given in the table below. There are changes in the assembler

instructions between the two processor core versions. There

are also some new instructions added in the M8C core.

These existing M8B instructions with equivalent M8C instruc-

tions and the new M8C instructions are tabulated in the

Appendix.

Some of the other important M8C changes not mentioned in

the table are:

■ The Carry and Zero flags have moved to a new FLAG

■ Because of the separate flag register, interrupts (and reti)

store (restore) three bytes instead of two.

■ The Interrupt Enable signal, previously handled with EI/DI

instructions, is now a bit in the flag register. Logical oper-

ations on the flag register perform the equivalent EI / DI

function.

■ Generally, most instructions have four new addressing

modes for a total of seven for each function.

Watchdog

In the CY7C64x13 microcontroller, the watchdog reset occurs

when the watchdog timer rolls over. Writing any value to

watchdog restart register (location 0x26) clears the timer. The

roll-over time for this timer is approximately 8 ms. Bit 6 of the

Processor and Control register (location 0xFF) registers this

event. Firmware must periodically (at least once every roll-

over time) clear this register for proper operation of the micro-

controller.

The CY7C64215’s watchdog is sourced by the internal low-

power oscillator or the 32.768 KHz external crystal oscillator.

Bit 7 of the OSC_CR0 register (location 1,E0h) is used for

this purpose. The watchdog period is configured using bits

Address

0x0000

0x1FDF

0x001A

12 Interrupt Vectors

+ 1 Reserved

Program Memory

Address

0x0000

CY7C64x13

14-bit Program Counter

CY7C64215

16-bit Program Counter

10 Interrupt Vectors

0x0040

0x0068

Program Memory

0x3FFF

0x002F

Feature M8B M8C

Accessing across 4K Boundary of 8K

ROM

Limited, can only ‘call’ from lower to upper 4K No limitations (LJMP, LCALL instructions)

ROM Size Access Limited to 8K Access up to 64K

RAM Size Access Limited to 256 bytes Access up to 4K (extended address bits, can be

divided between RAM and IO registers)

Instruction Set Irregular/non-orthogonal Many more instructions, nearly orthogonal

access

Program/Data Stack Two separate stacks, grow toward each other Single stack

Bit Test/Set/Clear No direct support Supported with expanded instruction set

Crossing 256-byte Page Boundaries Assembler inserts XPAGE automatically No XPAGE; micro adds one clock cycle on page

crossings

1 2 3 4 5 6 7 8 9 10 11 12 ... 15 16

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