Cypress Semiconductor enCoRe CY7C64215 Uživatelský manuál stáhnout pdf (Strana 2)

August 17, 2011 Document No. 001-15340 Rev. *A

AN6073

The CY7C64x13 has an integrated transceiver and can support five user configured endpoints—up to four 8-byte endpoints or

up to two 32-byte endpoints. It also conforms to USB specification v1.1 and USB HID specification v1.1. It is available in com-

mercial temperature range (0 to 70°C) and can operate from 4.0 V to 5.5 V DC.

Figure 1. Block Diagram of the CY7C64x13 Microcontroller

enCoRe III – CY7C64215 Microcontroller

This microcontroller integrates certain features that are nor-

mally added externally to USB micros. In addition it has con-

figurable peripherals and preconfigured system resource

blocks.

The CY7C64215 has an 8-bit Harvard Architecture Processor

with speeds up to 24 MHz and two 8x8 Multiply, 32-bit Accu-

mulate blocks. It has an operating voltage range from 3.0V to

5.25V and is built for commercial temperatures (0 to 70°C).

enCoRe III has four 8-bit digital peripherals as well as analog

peripherals with the following base capabilities:

■ Analog enCoRe III peripheral provides:

❐ Up to 14-bit incremental ADCs

■ Four digital enCoRe III peripherals provide:

❐ 8-bit PWMs

❐ Full-Duplex UART

❐ Multiple SPI Masters or Slaves

❐ Connectable to all GPIO Pins

These blocks are highly configurable and can be combined to

produce complex peripherals. For the developers’ conve-

nience a set of preconfigured functions is available with the

development tool in the form of selectable ‘User Modules’.

The enCoRe III’s program memory is flash based, which

makes it reprogrammable. It is also in-system programmable.

The flash supports partial updates made possible with

EEPROM emulation. enCoRe III’s flash also has four flexible

Logic Block Diagram

Interrupt

Controller

PROM

12-bit

Timer

Reset

Watchdog

Timer

Power-On

SCLK

GPIO

PORT 1

GPIO

PORT 0

P0[7:0]

P1[2:0]

P1[7:3]

SDATA

8-bit Bus

6-MHz crystal

RAM

USB

SIE

USB

Transceiver

D+[0]

D–[0]

Upstream

USB Port

P3[2:0]

High Current

Outputs

256 byte

8 KB

Clock

6 MHz

12-MHz

8-bit

CPU

C-compatible interface enabled by firmware through

Interface

P3[7:3]

Additional

Outputs

High Current

PLL

12 MHz

48 MHz

Divider

GPIO/

PORT 2

P2[0,1,7]

P2[3]; Data_Ready

P2[4]; STB

P2[5]; OE

P2[6]; CS

P2[2]; Latch_Empty

HAPI

P2[1:0] or P1[1:0]

PORT 3

GPIO

1 2 3 4 5 6 7 ... 15 16

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