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CY7C64215
Document Number: 38-08036 Rev. *E Page 30 of 33
Thermal Impedance
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 27. Thermal Impedance for the Package
Package Typical θ
JA
[13]
56 Pin QFN
[14]
20
o
C/W
28 Pin SSOP 96
o
C/W
Table 28. Solder Reflow Peak Temperature
Package Minimum Peak Temperature
[15]
Maximum Peak Temperature
56 Pin QFN 240°C 260°C
28 Pin SSOP 240°C 260°C
Package Handling
Some IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leaving
the factory. A label on the packaging has details about actual bake temperature and the minimum bake time to remove this moisture.
The maximum bake time is the aggregate time that the devices are exposed to the bake temperature. Exceeding this exposure time
may degrade device reliability.
Parameter Description Min Typ Max Unit
T
BAKETEMP
Bake Temperature 125 See Package Label °C
T
BAKETIME
Bake Time See Package Label 72 Hours
Notes
13. T
J
= T
A
+ POWER x θ
JA
14. To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the PCB ground plane.
15. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5°C with Sn-Pb or 245 ± 5°C with Sn-Ag-Cu paste.
Refer to the solder manufacturer specifications.
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