Cypress Semiconductor CY7C1480V25 Uživatelský manuál stáhnout pdf (Strana 15)

Chapter 2: Board Components 2–7

Featured Device: Stratix IV GT Device

September 2010 Altera Corporation 100G Development Kit, Stratix IV GT Edition Reference Manual

I/O Resources

Figure 2–2 shows the bank organization and I/O count for the EP4S100G5F45I1

device in the 1932-pin FBGA package.

Table 2–4 summarizes the FPGA I/O usage by function on the Stratix IV GT 100G

development board. I/O direction is with respect to the FPGA.

Figure 2–2. Stratix IV GT Device I/O Bank Diagram (Note 1)

Note to Figure 2–2:

(1) There are two additional PMA-only transceiver channels in each transceiver bank.

Bank 8B 48

Bank 7A 48

Bank 7B 48

Bank 7C 32

21 Bank 1C

21 Bank 2C

48 Bank 3B

48 Bank 4A

48 Bank 4B

32 Bank 4C

Bank 6C 22

Bank 5C 19

13 Bank 2A

Bank 8C 32

Bank 8A 48

32 Bank 3C

48 Bank 3A

Bank 5A 42

Bank 6A 38

Bank

Name

Number

of I/Os

Bank

Name

Number

of I/Os

40 Bank 1A

Bank

GXBL2

Bank

GXBL1

Bank

GXBL0

4 (1)

Bank

GXBR2

Bank

GXBR1

Bank

GXBR0

4 (1)

EP4S100G3

EP4S100G4

EP4S100G5

41 Bank 2B

Bank 5B 12

Table 2–4. Stratix IV GT I/O Usage Summary (Part 1 of 5)

Function I/O Type I/O Count Description

FPGA Transceiver Clocks

Reference clock from buffer LVDS input 12 Diff REFCLK input

Programmable clock LVDS input 2 Diff REFCLK input

SMA diff clock inputs LVDS input 6 Diff REFCLK input

FPGA Global Clocks

50-MHz clock 2.5-V CMOS input 1 Global clock

Ethernet receive clock 2.5-V CMOS input 1 Global clock

Single-ended clock from buffer 2.5-V CMOS input 4 Single-ended global clock

Differential clock from buffer LVDS input 4 Diff global clock

DDR3 clock from buffer LVDS input 8 Diff global clock

QDR II clock from buffer LVDS input 8 Diff global clock

1 2 ... 10 11 12 13 14 15 16 17 18 19 20 ... 79 80

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