Cypress Semiconductor MoBL-USB CY7C68000A Specifikace

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CY7C68000A
MoBL-USB™ TX2 USB 2.0 UTMI Transceiver
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document #: 38-08052 Rev. *H Revised May 22, 2009
MoBL-USB
TX2 Features
UTMI-Compliant and USB 2.0 Certified for Device Operation
Operates in Both USB 2.0 High Speed (HS), 480 Mbits/second,
and Full Speed (FS), 12 Mbits/second
Optimized for Seamless Interface with Intel
®
Monahans Appli-
cations Processors
Tristate Mode Enables Sharing of UTMI Bus with other Devices
Serial-to-Parallel and Parallel-to-Serial Conversions
8-bit Unidirectional, 8-bit Bidirectional, or 16-bit Bidirectional
External Data Interface
Synchronous Field and EOP Detection on Receive Packets
Synchronous Field and EOP Generation on Transmit Packets
Data and Clock Recovery from the USB Serial Stream
Bit Stuffing and Unstuffing; Bit Stuff Error Detection
Staging Register to Manage Data Rate Variation due to Bit
Stuffing and Unstuffing
16-bit 30 MHz and 8-bit 60 MHz Parallel Interface
Ability to Switch between FS and HS Terminations and
Signaling
Supports Detection of USB Reset, Suspend, and Resume
Supports HS Identification and Detection as defined by the USB
2.0 Specification
Supports Transmission of Resume Signaling
3.3V Operation
Two Package Options: 56-pin QFN and 56-pin VFBGA
All Required Terminations, Including 1.5 Kohm Pull Up on
DPLUS, are Internal to Chip
Supports USB 2.0 Test Modes
The Cypress MoBL-USB TX2 is a Universal Serial Bus (USB)
specification revision 2.0 transceiver, serial and deserializer, to a
parallel interface of either 16 bits at 30 MHz or eight bits at
60 MHz. The MoBL-USB TX2 provides a high speed physical
layer interface that operates at the maximum allowable USB 2.0
bandwidth. This enables the system designer to keep the
complex high speed analog USB components external to the
digital ASIC. This decreases development time and associated
risk. A standard USB 2.0-certified interface is provided and is
compliant with Transceiver Macrocell Interface (UTMI) specifi-
cation version 1.05 dated 3/29/2001.
This product is also optimized to seamlessly interface with
Monahans -P & -L applications processors. It has been charac-
terized by Intel and is recommended as the USB 2.0 UTMI trans-
ceiver of choice for its Monahans processors. It is also capable
of tristating the UTMI bus, while suspended, to enable the bus to
be shared with other devices.
Two packages are defined for the families: 56-pin QFN and
56-pin VFBGA.
The functional block diagram follows.
Tri_state
Logic Block Diagram
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Strany 1 - CY7C68000A

CY7C68000AMoBL-USB™ TX2 USB 2.0 UTMI TransceiverCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Documen

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CY7C68000ADocument #: 38-08052 Rev. *H Page 10 of 15AC Electrical CharacteristicsUSB 2.0 TransceiverUSB 2.0-compliant in FS and HS modes.Timing Diagra

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CY7C68000ADocument #: 38-08052 Rev. *H Page 11 of 15HS/FS Interface Timing - 30 MHzFigure 4. 30 MHz Timing Interface Timing ConstraintsFigure 5. Tri

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CY7C68000ADocument #: 38-08052 Rev. *H Page 12 of 15Ordering InformationOrdering Code Package TypeCY7C68000A-56LFXC 56 QFNCY7C68000A-56BAXC 56 VFBGACY

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CY7C68000ADocument #: 38-08052 Rev. *H Page 13 of 15PCB Layout RecommendationsFollow these recommendations to ensure reliable, high perfor-mance opera

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CY7C68000ADocument #: 38-08052 Rev. *H Page 14 of 15Quad Flat Package No Leads (QFN) Package Design NotesElectrical contact of the part to the Printed

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Document #: 38-08052 Rev. *H Revised May 22, 2009 Page 15 of 15MoBL-USB TX2 is a trademark of Cypress Semiconductor Corporation. Intel is a registered

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CY7C68000ADocument #: 38-08052 Rev. *H Page 2 of 15ApplicationsMobile Applications Smart Phones PDA Phones Gaming Phones MP3 players Portable Med

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CY7C68000ADocument #: 38-08052 Rev. *H Page 3 of 15Operational ModesThe operational modes are controlled by the OpMode signals.The OpMode signals are

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CY7C68000ADocument #: 38-08052 Rev. *H Page 4 of 15Pin ConfigurationsThe following pages illustrate the individual pin diagrams that are available in

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CY7C68000ADocument #: 38-08052 Rev. *H Page 5 of 15Figure 2. CY7C68000A 56-pin VFBGA Pin Assignment12345678ABCDEFGH1A 2A 3A 4A 5A 6A 7A 8A1B 2B 3B 4B

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CY7C68000ADocument #: 38-08052 Rev. *H Page 6 of 15Pin Descriptions Table 1. Pin DescriptionsQFN VFBGA Name Type Default Description[1]4H1AVCC PowerN

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CY7C68000ADocument #: 38-08052 Rev. *H Page 7 of 1524 B8 Tri_state Input Tri-state Mode Enable Places the CY7C68000A into Tri-state mode which tri-sta

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CY7C68000ADocument #: 38-08052 Rev. *H Page 8 of 1521 A4 RXValid Output Receive Data Valid This signal indicates that the DataOut bus has valid data.

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CY7C68000ADocument #: 38-08052 Rev. *H Page 9 of 15Absolute Maximum RatingsStorage Temperature ......... –65°C to +150°CAmbie

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