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Cypress Semiconductor Corporation
SL811HS and SL811HST: Application Notes
©2001 Cypress Semiconductor Corporation. All rights reserved. The information
and specifications contained in this document are subject to change without
notice.
Date: 07/26/01
Revision: 1.21
Page: 16
3.3. SL811HS MEMORY MAP
The SL811HS contains 256 bytes of internal memory buffer. The first 16 bytes of memory
represent control and status registers for programmed I/O operations. The remaining memory
locations are used for data buffering (max 240 Bytes).
The SL811HS can be mapped into the users processor I/O or memory space. In the following
example, which is used in the SL811HS DVK, The SL811HS is mapped at an ISA bus I/O
location.
Table 1: SL811HS and PC address
Register Name Address Register Function
Host Mode
SL11_ADDR 0x290
SL811HS I/O Address
Figure 3: SL811HS Internal Memory Map
Control Registers
(0x00-0x0F)
Memory Buffer
(0x10-0xff)
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