Cypress Semiconductor CY7C1386F Uživatelský manuál stáhnout pdf (Strana 27)

CY7C1386D, CY7C1386F

CY7C1387D, CY7C1387F

Document Number: 38-05545 Rev. *H Page 27 of 36

Figure 7. Read/Write Cycle Timing

[32, 33, 34]

Switching Waveforms (continued)

CYC

CLK

ADSP

ADH

ADS

ADDRESS

ADSC

CEH

CES

Data Out (Q)

High-Z

ADV

Single WRITE

D(A3)

A4 A5 A6

D(A5) D(A6)

Data In (D)

BURST READ

Back-to-Back READs

High-Z

Q(A2)Q(A1)

Q(A4)

WEH

WES

Q(A4+3)

OEHZ

OELZ

CLZ

Back-to-Back

WRITEs

BWE, BW X

DON’T CARE

UNDEFINED

Notes

32.

Full width write can be initiated by either GW

LOW, or by GW HIGH, BWE LOW, and BW

LOW.

33. The data bus (Q) remains in high Z following a Write cycle, unless a new read access is initiated by ADSP

or ADSC.

34. GW

is HIGH.

[+] Feedback

1 2 ... 22 23 24 25 26 27 28 29 30 31 32 ... 35 36

DCD Sync SRAM 1
CY7C1387F (1 M × 18) 5
CY7C1386F (512 K × 36) 5
Single Read Accesses 8
Burst Sequences 9
Sleep Mode 9
(MODE = Floating or V 10
CY7C1386D, CY7C1386F 11
CY7C1387D, CY7C1387F 11
Disabling the JTAG Feature 13
Test Access Port (TAP) 13
Performing a TAP Reset 13
TAP Registers 13
TAP Instruction Set 13
Ordering Code Definitions 29
Units of Measure 33
Products 36
PSoC Solutions 36

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