Cypress Semiconductor FX2LP Datový list stáhnout pdf (Strana 41)

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Document #: 38-08032 Rev. *V Page 41 of 66

9.4 Data Memory Write

Figure 9-3. Data Memory Write Timing Diagram

When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is only active while either RD#

or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the address valid time for which is based on

the stretch value.

OFF1

CLKOUT

A[15..0]

WR#

D[7..0]

STBL

STBH

data out

OFF1

CLKOUT

A[15..0]

WR#

D[7..0]

data out

Stretch = 1

ON1

SCSL

CS#

ON1

CS#

Table 16. Data Memory Write Parameters

Parameter Description Min Max Unit Notes

Delay from clock to valid address 0 10.7 ns –

STBL

Clock to WR pulse LOW 0 11.2 ns –

STBH

Clock to WR pulse HIGH 0 11.2 ns –

SCSL

Clock to CS pulse LOW – 13.0 ns –

ON1

Clock to data turn-on 0 13.1 ns –

OFF1

Clock to data hold time 0 13.1 ns –

1 2 ... 36 37 38 39 40 41 42 43 44 45 46 ... 65 66

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Cypress Semiconductor FX2LP Datový list Strana 41