Cypress Semiconductor CY7C1522AV18 Uživatelský manuál stáhnout pdf

72-Mbit DDR-II SIO SRAM 2-Word

Burst Architecture

CY7C1522AV18, CY7C1529AV18

CY7C1523AV18, CY7C1524AV18

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 001-06981 Rev. *C Revised September 14, 2007

Features

■ 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)

■ 300 MHz clock for high bandwidth

■ 2-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces

(data transferred at 600 MHz) at 300 MHz

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Synchronous internally self-timed writes

■ DDR-II operates with 1.5 cycle read latency when the DLL is

enabled

■ Operates similar to a DDR-I device with 1 cycle read latency in

DLL off mode

■ 1.8V core power supply with HSTL inputs and outputs

■ Variable drive HSTL output buffers

■ Expanded HSTL output voltage (1.4V–V

)

■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1522AV18 – 8M x 8

CY7C1529AV18 – 8M x 9

CY7C1523AV18 – 4M x 18

CY7C1524AV18 – 2M x 36

Functional Description

The CY7C1522AV18, CY7C1529AV18, CY7C1523AV18, and

CY7C1524AV18 are 1.8V Synchronous Pipelined SRAMs,

equipped with Double Data Rate Separate IO (DDR-II SIO)

architecture. The DDR-II SIO consists of two separate ports: the

read port and the write port to access the memory array. The

read port has data outputs to support read operations and the

write port has data inputs to support write operations. The DDR-II

SIO has separate data inputs and data outputs to completely

eliminate the need to “turn-around” the data bus required with

common IO devices. Access to each port is accomplished

through a common address bus. Addresses for read and write

are latched on alternate rising edges of the input (K) clock. Write

data is registered on the rising edges of both K and K

. Read data

is driven on the rising edges of C and C if provided, or on the

rising edge of K and K

if C/C are not provided. Each address

location is associated with two 8-bit words in the case of

CY7C1522AV18, two 9-bit words in the case of CY7C1529AV18,

two 18-bit words in the case of CY7C1523AV18, and two 36-bit

words in the case of CY7C1524AV18 that burst sequentially into

or out of the device.

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs are tightly matched to the

two output echo clocks CQ/CQ

, eliminating the need to capture

data separately from each individual DDR-II SIO SRAM in the

system design. Output data clocks (C/C

) enable maximum

system clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the C or C

(or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

Selection Guide

Description 300 MHz 278 MHz 250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 300 278 250 200 167 MHz

Maximum Operating Current x8 900 855 800 700 650 mA

x9 900 855 800 700 650

x18 950 880 800 700 650

x36 1080 1000 900 750 650

[+] Feedback [+] Feedback

1 2 3 4 5 6 ... 29 30

Shrnutí obsahu

Strany 1 - Burst Architecture

72-Mbit DDR-II SIO SRAM 2-WordBurst ArchitectureCY7C1522AV18, CY7C1529AV18CY7C1523AV18, CY7C1524AV18Cypress Semiconductor Corporation • 198 Champion C

Strany 2

CY7C1522AV18, CY7C1529AV18CY7C1523AV18, CY7C1524AV18Document #: 001-06981 Rev. *C Page 10 of 30Truth TableThe truth table for CY7C1522AV18, CY7C1529AV

Strany 3

CY7C1522AV18, CY7C1529AV18CY7C1523AV18, CY7C1524AV18Document #: 001-06981 Rev. *C Page 11 of 30Write Cycle DescriptionsThe write cycle description tab

Strany 4

CY7C1522AV18, CY7C1529AV18CY7C1523AV18, CY7C1524AV18Document #: 001-06981 Rev. *C Page 12 of 30IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs inco

Strany 5

CY7C1522AV18, CY7C1529AV18CY7C1523AV18, CY7C1524AV18Document #: 001-06981 Rev. *C Page 13 of 30IDCODEThe IDCODE instruction loads a vendor-specific, 3

Strany 6

CY7C1522AV18, CY7C1529AV18CY7C1523AV18, CY7C1524AV18Document #: 001-06981 Rev. *C Page 14 of 30TAP Controller State DiagramThe state diagram for the T

Strany 7

CY7C1522AV18, CY7C1529AV18CY7C1523AV18, CY7C1524AV18Document #: 001-06981 Rev. *C Page 15 of 30TAP Controller Block DiagramTAP Electrical Characterist

Strany 8

CY7C1522AV18, CY7C1529AV18CY7C1523AV18, CY7C1524AV18Document #: 001-06981 Rev. *C Page 16 of 30TAP AC Switching Characteristics Over the Operating Ran

Strany 9

CY7C1522AV18, CY7C1529AV18CY7C1523AV18, CY7C1524AV18Document #: 001-06981 Rev. *C Page 17 of 30Identification Register Definitions Instruction FieldVa

Strany 10 - CY7C1523AV18, CY7C1524AV18

CY7C1522AV18, CY7C1529AV18CY7C1523AV18, CY7C1524AV18Document #: 001-06981 Rev. *C Page 18 of 30Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # B

Strany 11

CY7C1522AV18, CY7C1529AV18CY7C1523AV18, CY7C1524AV18Document #: 001-06981 Rev. *C Page 19 of 30Power Up Sequence in DDR-II SRAMDDR-II SRAMs must be po

Strany 12

CY7C1522AV18, CY7C1529AV18CY7C1523AV18, CY7C1524AV18Document #: 001-06981 Rev. *C Page 2 of 30Logic Block Diagram (CY7C1522AV18)Logic Block Diagram (C

Strany 13

CY7C1522AV18, CY7C1529AV18CY7C1523AV18, CY7C1524AV18Document #: 001-06981 Rev. *C Page 20 of 30Maximum RatingsExceeding maximum ratings may impair the

Strany 14

CY7C1522AV18, CY7C1529AV18CY7C1523AV18, CY7C1524AV18Document #: 001-06981 Rev. *C Page 21 of 30IDD VDD Operating Supply VDD = Max,IOUT = 0 mA,f = fMAX

Strany 15

CY7C1522AV18, CY7C1529AV18CY7C1523AV18, CY7C1524AV18Document #: 001-06981 Rev. *C Page 22 of 30CapacitanceTested initially and after any design or pro

Strany 16 - [+] Feedback [+] Feedback

CY7C1522AV18, CY7C1529AV18CY7C1523AV18, CY7C1524AV18Document #: 001-06981 Rev. *C Page 23 of 30Switching Characteristics Over the Operating Range [19,

Strany 17

CY7C1522AV18, CY7C1529AV18CY7C1523AV18, CY7C1524AV18Document #: 001-06981 Rev. *C Page 24 of 30Output TimestCOtCHQVC/C Clock Rise (or K/K in single cl

Strany 18

CY7C1522AV18, CY7C1529AV18CY7C1523AV18, CY7C1524AV18Document #: 001-06981 Rev. *C Page 25 of 30Switching WaveformsFigure 3. Read/Write/Deselect Seque

Strany 19 - Power Up Waveforms

CY7C1522AV18, CY7C1529AV18CY7C1523AV18, CY7C1524AV18Document #: 001-06981 Rev. *C Page 26 of 30Ordering Information Not all of the speed, package and

Strany 20 - Operating Range

CY7C1522AV18, CY7C1529AV18CY7C1523AV18, CY7C1524AV18Document #: 001-06981 Rev. *C Page 27 of 30250 CY7C1522AV18-250BZC 51-85195 165-Ball Fine Pitch Ba

Strany 21

CY7C1522AV18, CY7C1529AV18CY7C1523AV18, CY7C1524AV18Document #: 001-06981 Rev. *C Page 28 of 30167 CY7C1522AV18-167BZC 51-85195 165-Ball Fine Pitch Ba

Strany 22 - AC Test Loads and Waveforms

CY7C1522AV18, CY7C1529AV18CY7C1523AV18, CY7C1524AV18Document #: 001-06981 Rev. *C Page 29 of 30Package DiagramFigure 4. 165-Ball FBGA (15 x 17 x 1.4 m

Strany 23

CY7C1522AV18, CY7C1529AV18CY7C1523AV18, CY7C1524AV18Document #: 001-06981 Rev. *C Page 3 of 30Logic Block Diagram (CY7C1523AV18)Logic Block Diagram (C

Strany 24

Document #: 001-06981 Rev. *C Revised September 14, 2007 Page 30 of 30QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by

Strany 25 - Switching Waveforms

CY7C1522AV18, CY7C1529AV18CY7C1523AV18, CY7C1524AV18Document #: 001-06981 Rev. *C Page 4 of 30Pin Configuration The pin configuration for CY7C1522AV18

Strany 26

CY7C1522AV18, CY7C1529AV18CY7C1523AV18, CY7C1524AV18Document #: 001-06981 Rev. *C Page 5 of 30CY7C1523AV18 (4M x 18)1234567891011A CQNC/144M A R/W BWS

Strany 27

CY7C1522AV18, CY7C1529AV18CY7C1523AV18, CY7C1524AV18Document #: 001-06981 Rev. *C Page 6 of 30Pin Definitions Pin Name IO Pin DescriptionD[x:0]Input-S

Strany 28

CY7C1522AV18, CY7C1529AV18CY7C1523AV18, CY7C1524AV18Document #: 001-06981 Rev. *C Page 7 of 30CQ Echo Clock CQ Referenced with Respect to C. This is a

Strany 29 - Package Diagram

CY7C1522AV18, CY7C1529AV18CY7C1523AV18, CY7C1524AV18Document #: 001-06981 Rev. *C Page 8 of 30Functional OverviewThe CY7C1522AV18, CY7C1529AV18, CY7C1

Strany 30

CY7C1522AV18, CY7C1529AV18CY7C1523AV18, CY7C1524AV18Document #: 001-06981 Rev. *C Page 9 of 30synchronized to the output clock of the DDR-II. In the s

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